Transistor with a primary gate wrapping a floating secondary gate

Abstract

Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.

What is claimed is: 
     
         1 . A structure comprising:
 a substrate; and   a transistor on the substrate, wherein the transistor includes:   a barrier layer;   a secondary gate on the barrier layer and having opposing sidewalls; and   a primary gate having first portions on the barrier layer and positioned laterally adjacent to the opposing sidewalls, respectively.   
     
     
         2 . The structure of  claim 1 , wherein the secondary gate is a floating gate. 
     
     
         3 . The structure of  claim 1 , wherein the secondary gate includes a P-type III-V semiconductor layer. 
     
     
         4 . The structure of  claim 3 , wherein the P-type III-V semiconductor layer includes a magnesium-doped gallium nitride layer. 
     
     
         5 . The structure of  claim 3 , wherein the primary gate includes: a gate dielectric layer immediately adjacent to the barrier layer and further extending over and immediately adjacent to the secondary gate; and a gate conductor layer on the gate dielectric layer. 
     
     
         6 . The structure of  claim 5 , wherein the gate dielectric layer includes a high dielectric constant material, and the gate conductor layer includes a metallic gate conductor material. 
     
     
         7 . The structure of  claim 1 , wherein the transistor further includes:
 a channel layer, wherein the barrier layer is on the channel layer; and   source and drain terminals extending at least partially through the barrier layer toward the channel layer, wherein the primary gate and the secondary gate are positioned laterally between the source and drain terminals.   
     
     
         8 . The structure of  claim 1 ,
 wherein the secondary gate further includes a top surface and opposing end walls,   wherein the primary gate further has a second portion on the top surface of the secondary gate and third portions positioned laterally adjacent to the opposing end walls of the secondary gate, and   wherein the structure further includes:
 a dielectric layer covering the primary gate; and 
 isolation regions below the opposing end walls of the secondary gate, extending vertically through the barrier layer into a channel layer, and extending laterally beyond the third portions of the primary gate. 
   
     
     
         9 . The structure of  claim 1 ,
 wherein the secondary gate further has a top surface and opposing end walls,   wherein the primary gate further has a second portion on the top surface of the secondary gate, and   wherein the structure further includes:
 a dielectric layer immediately adjacent to the opposing end walls of the secondary gate and further covering the primary gate; and 
 isolation regions below the opposing end walls and extending vertically through the barrier layer into a channel layer. 
   
     
     
         10 . A structure comprising:
 a substrate; and   a transistor on the substrate, wherein the transistor includes:
 a barrier layer; 
 a secondary gate on the barrier layer and having opposing sidewalls, opposing end walls and a top surface, wherein the secondary gate includes a P-type III-V semiconductor layer and is floating; and 
 a primary gate including:
 a gate dielectric layer immediately adjacent to the barrier layer and further extending over and immediately adjacent to the opposing sidewalls, the opposing end walls, and the top surface of the secondary gate; and 
 a gate conductor layer on the gate dielectric layer, 
 
 wherein the primary gate has first portions on the barrier layer and positioned laterally adjacent to the opposing sidewalls, respectively, of the secondary gate, a second portion on the top surface of the secondary gate, and third portions on the barrier layer and positioned laterally adjacent to the opposing end walls, respectively, of the secondary gate. 
   
     
     
         11 . A method comprising:
 providing a substrate; and   forming a transistor on the substrate, wherein the forming of the transistor includes:
 forming a secondary gate on a barrier layer; and 
 forming a primary gate having first portions on the barrier layer and positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. 
   
     
     
         12 . The method of  claim 11 , wherein the forming of the secondary gate includes:
 forming a P-type III-V semiconductor layer on the barrier layer; and   forming, from the P-type III-V semiconductor layer, an essentially rectangular-shaped semiconductor body to form the secondary gate.   
     
     
         13 . The method of  claim 12 , wherein the P-type III-V semiconductor layer includes a magnesium-doped gallium nitride layer. 
     
     
         14 . The method of  claim 11 , wherein the forming of the transistor further includes forming isolation regions in the barrier layer below opposing end walls of the secondary gate and extending vertically through the barrier layer into a channel layer. 
     
     
         15 . The method of  claim 11 , wherein the forming of the primary gate includes:
 forming a gate dielectric layer immediately adjacent to the barrier layer and further extending over and immediately adjacent to the opposing sidewalls, opposing end walls, and a top surface of the secondary gate;   forming a gate conductor layer on the gate dielectric layer to form a gate stack; and   patterning the gate stack to form the primary gate.   
     
     
         16 . The method of  claim 15 , wherein the patterning is performed such that the primary gate has the first portions positioned laterally adjacent to the opposing sidewalls, respectively, of the secondary gate, a second portion on the top surface of the secondary gate, and third portions positioned laterally adjacent to the opposing end walls, respectively, of the secondary gate. 
     
     
         17 . The method of  claim 15 , wherein the patterning is performed such that the primary gate has the first portions positioned laterally adjacent to the opposing sidewalls, respectively, of the secondary gate and a second portion on the top surface of the secondary gate and further such that the opposing end walls, respectively, of the secondary gate are exposed. 
     
     
         18 . The method of  claim 15 , wherein the gate dielectric layer includes a high dielectric constant material, and the gate conductor layer includes a metallic gate conductor material. 
     
     
         19 . The method of  claim 11 , further including performing middle of the line processing, wherein the performing of the middle of the line processing does not include forming contacts to the secondary gate so the secondary gate remains floating. 
     
     
         20 . The method of  claim 11 , wherein the forming of the transistor further includes:
 forming a channel layer;   forming the barrier layer on the channel layer; and   forming source and drain terminals extending at least partially through the barrier layer toward the channel layer, wherein the primary gate and the secondary gate are positioned laterally between the source and drain terminals.