Self-aligned zero track skip

Abstract

A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

1 . A semiconductor structure comprising:
 a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment; and   a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring;   wherein a distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the second level interconnect wiring is subtractively patterned to define a positive tapered angle. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein outer surfaces of the first and second line segments are self-aligned to corresponding outer surfaces of the second level interconnect wiring. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein a capping layer is disposed over and in direct contact with the second level interconnect wiring. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein the capping layer defines a first positive tapered angle. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein an etch-resistant liner is disposed on sidewalls of the second level interconnect wiring and sidewalls of the capping layer. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein the etch-resistant liner defines a second positive tapered angle. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein the separation of the first level of interconnect wiring into the first interconnect wiring segment and the second interconnect wiring segment occurs directly between the second level interconnect wiring. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the first level of interconnect wiring exhibits a self-aligned cut having a width within the spacing of the second level interconnect wiring. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein a via connecting the first level of interconnect wiring to the second level of interconnect wiring is larger than the spacing of the second level interconnect wiring. 
     
     
         11 . A semiconductor structure comprising:
 a first level of interconnect wiring exhibiting a self-aligned cut; and   a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring;   wherein the first level of interconnect wiring is split into two segments to define a pair of line segments with tip-to-tip spacing less than or equal to a spacing of the second level interconnect wiring.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein the tip-to-tip spacing defines a zero track skip. 
     
     
         13 . The semiconductor structure of  claim 11 , wherein the self-aligned cut has a width dimensioned within the spacing of the second level interconnect wiring. 
     
     
         14 . The semiconductor structure of  claim 11 , wherein outer surfaces of the pair of line segments are self-aligned to corresponding outer surfaces of the second level interconnect wiring. 
     
     
         15 . The semiconductor structure of  claim 11 , wherein a capping layer is disposed over and in direct contact with the second level interconnect wiring. 
     
     
         16 . The semiconductor structure of  claim 15 , wherein the capping layer defines a first positive tapered angle. 
     
     
         17 . The semiconductor structure of  claim 16 , wherein an etch-resistant liner is disposed on sidewalls of the second level interconnect wiring and sidewalls of the capping layer. 
     
     
         18 . The semiconductor structure of  claim 17 , wherein the etch-resistant liner defines a second positive tapered angle. 
     
     
         19 . A method comprising:
 forming a first level of interconnect wiring;   forming a second level interconnect wiring orthogonally to the first level of interconnect wiring by using subtractive etching;   disposing a capping layer over and in direct contact with the second level interconnect wiring;   disposing an etch-resistant liner on sidewalls of the second level interconnect wiring and sidewalls of the capping layer;   depositing a litho mask; and   creating an opening through the litho mask and between the second level interconnect wiring to separate the first level of interconnect wiring into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment;   wherein a distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.   
     
     
         20 . The method of  claim 19 , wherein outer surfaces of the first and second line segments are self-aligned to corresponding outer surfaces of the second level interconnect wiring.