Memory device

Abstract

A memory device includes: a word line stack including word lines that are alternately stacked vertically over a substrate, and having an edge portion; at least one supporter extending vertically in a direction that the word lines are stacked and supporting the edge portion of the word line stack; contact plugs that are electrically connected to the word lines at the edge portion of the word line stack; and active layers positioned between the word lines, and horizontally oriented in a direction intersecting with the word lines.

What is claimed is: 
     
         1 . A memory device, comprising:
 an array of vertically stacked memory cells comprising a vertical stack of horizontally oriented conductive lines, which comprises a first step structure and a second step structure opposite the first step structure, each of the first and second step structures including a first sidewall and a second sidewall parallel to the first sidewall;   a plurality of dielectric pillars supporting the first and second step structures of the vertical stack, and being spaced apart from each other along at least one sidewall among the first and second sidewalls; and   active layers positioned between the horizontally oriented conductive lines, and horizontally oriented in a direction intersecting with the horizontally oriented conductive lines.   
     
     
         2 . The memory device of  claim 1 , further comprising:
 a vertically oriented conductive line commonly coupled to one side of the active layers, the vertically oriented conductive line extending in a direction in which the horizontally oriented conductive lines are stacked.   
     
     
         3 . The memory device of  claim 2 , further comprising:
 storage elements respectively coupled to another side of the active layers, and vertically stacked in a direction in which the horizontally oriented conductive lines are stacked.   
     
     
         4 . The memory device of  claim 1 , wherein each of the horizontally oriented conductive lines includes:
 an upper conductive line disposed over an upper surface of the active layers; and   a lower conductive line disposed over a lower surface of the active layers.   
     
     
         5 . The memory device of  claim 1 , wherein the plurality of dielectric pillars directly contacts at least one sidewall among the first and second sidewalls. 
     
     
         6 . The memory device of  claim 1 , wherein each of the first sidewall and the second sidewall includes at least one recess surface which extends vertically in a direction in which the horizontally oriented conductive lines are stacked, the at least one recess surface directly contacting the at least one supporter. 
     
     
         7 . The memory device of  claim 1 , wherein the at least one supporter includes silicon oxide.