Integrated circuit package and method

Abstract

A semiconductor device includes a first semiconductor package comprising: a first interconnect structure on a first semiconductor substrate; through substrate vias electrically coupled to the first interconnect structure extending through the first semiconductor substrate; and a second semiconductor package directly bonded to the first semiconductor package, the second semiconductor package comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate. The semiconductor device further includes a silicon layer on a surface of the second semiconductor package that is opposite to the first semiconductor package; and a heat dissipation structure attached to the silicon layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first semiconductor package comprising:   a first interconnect structure on a first semiconductor substrate;   through substrate vias electrically coupled to the first interconnect structure extending through the first semiconductor substrate; and   a second semiconductor package directly bonded to the first semiconductor package, the second semiconductor package comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate; and   a silicon layer on a side of the second semiconductor package that is opposite to the first semiconductor package; and   a heat dissipation structure attached to the silicon layer.   
     
     
         2 . The device of  claim 1 , wherein the silicon layer has a thickness in a range from 1 μm to 6 μm. 
     
     
         3 . The device of  claim 1 , further comprising:
 a first oxide bonding layer in direct physical contact with the silicon layer; and   a second oxide bonding layer in direct physical contact with the first oxide bonding layer, the second oxide bonding layer being in physical contact with the heat dissipation structure.   
     
     
         4 . The device of  claim 1 , further comprising a metal bonding layer directly bonded to the silicon layer, the metal bonding layer being in direct physical contact with the heat dissipation structure. 
     
     
         5 . The device of  claim 1 , wherein the second semiconductor package further comprises an insulating buffer layer on the second semiconductor substrate, the insulating buffer layer being in direct physical contact with the silicon layer. 
     
     
         6 . The device of  claim 1 , wherein the second semiconductor package further comprises a plurality of dummy dies, the dummy dies adjacent to the second semiconductor die. 
     
     
         7 . The device of  claim 1 , wherein the first semiconductor package is directly bonded to the second semiconductor package by a bonding layer, the bonding layer comprising:
 bonding pads electrically coupling the first semiconductor die to the second semiconductor die; and   dummy pads.   
     
     
         8 . A method of manufacturing a semiconductor device comprising:
 forming a first bonding layer over a first semiconductor die, the first semiconductor die comprising a first interconnect structure on a first semiconductor substrate;   bonding a second semiconductor die to the first bonding layer, the second semiconductor die comprising a second interconnect structure on a second semiconductor substrate;   encapsulating the second semiconductor die in an encapsulant;   depositing an insulating buffer layer over the second semiconductor die and the encapsulant;   forming a second bonding layer over a top surface of the second semiconductor die and the encapsulant, wherein the second bonding layer has a higher thermal conductivity than the insulating buffer layer; and   directly bonding a third bonding layer of a heat dissipation structure to the second bonding layer, wherein the heat dissipation structure comprises the third bonding layer on a silicon substrate.   
     
     
         9 . The method of  claim 8 , wherein the forming the second bonding layer comprises depositing a silicon layer over the insulating buffer layer and bonding the third bonding layer to the silicon layer. 
     
     
         10 . The method of  claim 9 , wherein the bonding the third bonding layer of the heat dissipation structure to the silicon layer comprises forming a metal-to-silicon bond between the silicon layer and the third bonding layer. 
     
     
         11 . The method of  claim 10 , wherein following forming the metal-to-silicon bond between the silicon layer and the third bonding layer, the silicon layer and the third bonding layer have a combined thickness between 1 μm to 6 μm. 
     
     
         12 . The method of  claim 9 , wherein the silicon layer has a thickness in a range from 1 μm to 6 μm. 
     
     
         13 . The method of  claim 8 , wherein the second bonding layer comprises a first metal layer and the third bonding layer comprises a second metal layer, and wherein the bonding the third bonding layer to the second bonding layer forms a metal-to-metal bond. 
     
     
         14 . The method of  claim 8 , wherein the first bonding layer comprises active bonding pads and dummy bonding pads, wherein the active bonding pads are used in the bonding the second semiconductor die to the first bonding layer and the active bonding pads electrically couple the first semiconductor die to the second semiconductor die. 
     
     
         15 . A method of manufacturing a semiconductor device comprising:
 bonding a first semiconductor die to a first carrier substrate, the first semiconductor die comprising:   a first interconnect structure, a first semiconductor substrate over the first interconnect structure; and   through substrate vias extending from the first interconnect structure through the first semiconductor substrate;   bonding a second semiconductor die to the first semiconductor die, the second semiconductor die comprising:   a second interconnect structure, and   a second semiconductor substrate over the second interconnect structure encapsulating the second semiconductor die in a molding compound;   depositing a silicon layer over the molding compound and the second semiconductor die;   bonding a second carrier substrate to the silicon layer; and   performing a debonding process to release the first carrier substrate from the first semiconductor die.   
     
     
         16 . The method of  claim 15 , further comprising:
 following the debonding process exposing a conductive contact pad of the first interconnect structure; and   forming an under-bump metallization in contact with the conductive contact pad.   
     
     
         17 . The method of  claim 15 , wherein the bonding the second carrier substrate to the silicon layer comprises:
 depositing a first oxide layer on the silicon layer;   depositing a second oxide layer on the second carrier substrate; and   directly bonding the first oxide layer to the second oxide layer.   
     
     
         18 . The method of  claim 17 , wherein bonding the second carrier substrate to the silicon layer further comprises activating a first surface of the first oxide layer or activating a second surface of the second oxide layer prior to directly bonding the first oxide layer to the second oxide layer. 
     
     
         19 . The method of  claim 15 , wherein the bonding the second semiconductor die to the first semiconductor die further comprises bonding contact pads of the second interconnect structure to metal bond pads, the metal bond pads being in direct physical contact with the through substrate vias and electrically coupling the first semiconductor die to the second semiconductor die. 
     
     
         20 . The method of  claim 15 , wherein bonding the second carrier substrate comprises a bonding a metal layer directly to the silicon layer, wherein the metal layer contacts the second carrier substrate.