Enlarged overlap between backside power rail and backside contact

Abstract

A first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact. Forming a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, where the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, wherein   the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a second backside power rail directly below and connected to a second source-drain epitaxy region of a negative field effect transistor (n-FET) region via a second backside contact vertically aligned with the second source-drain epitaxy region, wherein   the second backside power rail directly contacts an upper horizontal surface of the second backside contact and the second backside power rail directly contacts a vertical side surface of the second backside contact.   
     
     
         3 . The semiconductor device according to  claim 2 , further comprising:
 a high-k dielectric spacer between the first backside power rail and the second backside power rail, wherein the high-k dielectric spacer comprises a k value of greater than 5.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein
 the high-k dielectric spacer is between the n-FET region and the p-FET region.   
     
     
         5 . The semiconductor device according to  claim 2 , further comprising:
 the p-FET region comprising semiconductor channel layers vertically aligned and stacked one on top of another, the semiconductor channel layers separated from each other by a gate stack material wrapped around the semiconductor channel layers; and   the n-FET region comprising semiconductor channel layers vertically aligned and stacked one on top of another, the semiconductor channel layers separated from each other by a gate stack material wrapping around the semiconductor channel layers.   
     
     
         6 . The semiconductor device according to  claim 1 , further comprising:
 a gate cut dielectric between adjacent stacks of semiconductor channel layers within the p-FET region.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein
 the gate cut dielectric comprises a different material than a shallow trench isolation region between the adjacent stacks of semiconductor channel layers within the p-FET region.   
     
     
         8 . The semiconductor device according to  claim 2 , further comprising:
 a dielectric pillar between the p-FET region and the n-FET region.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein
 the dielectric pillar extends vertically into a substrate of the semiconductor device.   
     
     
         10 . The semiconductor device according to  claim 1 , wherein
 a vertical contact area between the first backside contact and the first backside power rail is greater than a horizontal contact area between the first backside contact and the first backside power rail.   
     
     
         11 . A semiconductor device comprising:
 a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, wherein   the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact; and   a second backside power rail directly below and connected to a second source-drain epitaxy region of a negative field effect transistor (n-FET) region via a second backside contact vertically aligned with the second source-drain epitaxy region, wherein   the second backside power rail directly contacts an upper horizontal surface of the second backside contact and the second backside power rail directly contacts a vertical side surface of the second backside contact.   
     
     
         12 . The semiconductor device according to  claim 11 , further comprising:
 a gate cut dielectric between adjacent stacks of semiconductor channel layers within the p-FET region.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein
 the gate cut dielectric comprises a different material than a shallow trench isolation region between adjacent stacks of semiconductor channel layers within the p-FET region.   
     
     
         14 . The semiconductor device according to  claim 11 , wherein
 a vertical contact area between the first backside contact and the first backside power rail is greater than a horizontal contact area between the first backside contact and the first backside power rail.   
     
     
         15 . A method comprising:
 forming a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, wherein   the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.   
     
     
         16 . The method according to  claim 15 , further comprising:
 forming a second backside power rail directly below and connected to a second source-drain epitaxy region of a negative field effect transistor (n-FET) region via a second backside contact vertically aligned with the second source-drain epitaxy region, wherein   the second backside power rail directly contacts an upper horizontal surface of the second backside contact and the second backside power rail directly contacts a vertical side surface of the second backside contact.   
     
     
         17 . The method according to  claim 16 , further comprising:
 forming a high-k dielectric spacer between the first backside power rail and the second backside power rail, wherein the high-k dielectric spacer comprises a k value of greater than 5, wherein   the high-k dielectric spacer is between the n-FET region and the p-FET region.   
     
     
         18 . The method according to  claim 16 , wherein
 the p-FET region comprising semiconductor channel layers vertically aligned and stacked one on top of another, the semiconductor channel layers separated from each other by a gate stack material wrapping around the semiconductor channel layers; and   the n-FET region comprising semiconductor channel layers vertically aligned and stacked one on top of another, the semiconductor channel layers separated from each other by a gate stack material wrapping around the semiconductor channel layers.   
     
     
         19 . The method according to  claim 14 , further comprising:
 forming a gate cut dielectric between adjacent stacks of semiconductor channel layers within the p-FET region, wherein   the gate cut dielectric comprises a different material than a shallow trench isolation region between adjacent stacks of semiconductor channel layers within the p-FET region.   
     
     
         20 . The method according to  claim 16 , wherein
 a vertical contact area between the first backside contact and the first backside power rail is greater than a horizontal contact area between the first backside contact and the first backside power rail.