Method of forming patterns of semiconductor device

Abstract

A method of forming a pattern of a semiconductor device, the method comprising forming an insulating film on a substrate having a first region and a second region, sequentially forming a lower mask layer and an upper mask layer on the insulating film, forming a line-shaped hard mask pattern having a plurality of narrow openings having the same width in the first region and the second region, respectively, on the upper mask layer, forming line-shaped spacers on sidewalls of the opening of the line-shaped hard mask pattern, forming a composite mask pattern composed of the spacer and a pattern having a first width among the line-shaped hard mask pattern by removing a pattern having a second width among the line-shaped hard mask patterns, the second width being smaller than the first width.

What is claimed is: 
     
         1 . A method of forming a pattern of a semiconductor device, the method comprising:
 forming an insulating film on a substrate having a first region and a second region;   sequentially forming a lower mask layer and an upper mask layer on the insulating film;   forming a line-shaped hard mask pattern having a plurality of narrow openings having the same width in the first region and the second region, respectively, on the upper mask layer;   forming line-shaped spacers on sidewalls of the plurality of narrow openings of the line-shaped hard mask pattern;   forming a composite mask pattern composed of the spacer and a pattern having a first width among the line-shaped hard mask pattern by removing a pattern having a second width among the line-shaped hard mask patterns, the second width being smaller than the first width;   forming a lower mask pattern by sequentially etching the upper mask layer and the lower mask layer using the composite mask pattern as an etch mask;   etching the insulating film using the lower mask pattern as an etching mask into a line-shaped insulating pattern having the same plurality of narrow openings in each of the first region and the second region;   forming a wide opening by removing a pattern having a third width among the line-shaped insulating patterns in the first region, and maintaining the plurality of narrow openings of the line-shaped insulating pattern in the second region;   forming a conductive material layer filling the wide opening and the plurality of narrow openings of the line-shaped insulating pattern; and   polishing the conductive material layer into a wide conductive line in the first region and a narrow conductive line in the second region.   
     
     
         2 . The method as claimed in  claim 1 , wherein:
 the wide conductive line and the narrow conductive line each have a tapered shape in which the width narrows towards the substrate, and   a first angle between an outer wall of the wide conductive line and an upper surface of the substrate is substantially equal to a second angle between the outer wall of the narrow conductive line and the upper surface of the substrate.   
     
     
         3 . The method as claimed in  claim 1 , wherein, in the first region, the wide opening is formed by removing a line-shaped insulating spacer pattern between the plurality of narrow openings. 
     
     
         4 . The method as claimed in  claim 3 , wherein:
 a first sidewall of the wide opening is located at a first outermost part of the plurality of narrow openings, and   a second sidewall of the wide opening is located at a second outermost part of the plurality of narrow openings.   
     
     
         5 . The method as claimed in  claim 3 , wherein the third width of the wide opening is determined by the number of removed line-shaped insulating spacer patterns between the plurality of narrow openings. 
     
     
         6 . The method as claimed in  claim 5 , wherein the third width of the wide opening increases or decreases as a multiple of a line-and-space width of the plurality of narrow openings. 
     
     
         7 . The method as claimed in  claim 1 , wherein the forming of the spacer includes:
 forming a preliminary spacer layer conformally covering the upper mask layer and the line-shaped hard mask pattern; and   performing an entire surface etching process on the preliminary spacer layer.   
     
     
         8 . The method as claimed in  claim 7 , wherein the material constituting the composite mask pattern is a dissimilar material having different etching selectivity from the pattern having the second width among the line-shaped hard mask patterns. 
     
     
         9 . The method as claimed in  claim 1 , wherein the forming of the conductive material layer is performed by a damascene process. 
     
     
         10 . The method as claimed in  claim 1 , wherein a conductive vertical via is under the wide conductive line. 
     
     
         11 . A method of forming a pattern of a semiconductor device, the method comprising:
 forming an insulating film on a substrate;   forming a lower mask layer on the insulating film;   forming a line-shaped hard mask pattern having an opening on the lower mask layer;   forming line-shaped spacers on sidewalls of the opening of the line-shaped hard mask pattern;   forming a composite mask pattern composed of the spacer and a pattern having a first width among the line-shaped hard mask patterns by removing a pattern having a second width among the line-shaped hard mask patterns, the second width being smaller than the first width;   forming a lower mask pattern by etching the lower mask layer using the composite mask pattern as an etch mask;   forming a line-shaped insulating pattern with a plurality of narrow openings each having a same fourth width by etching the insulating film using the lower mask pattern as an etching mask;   forming a wide opening by removing a pattern having a third width among the line-shaped insulating patterns;   forming a conductive material layer filling the wide opening of the line-shaped insulating pattern; and   polishing the conductive material layer into a wide conductive line.   
     
     
         12 . The method as claimed in  claim 11 , wherein:
 the wide conductive line has a tapered shape that narrows towards the substrate, and   a first angle between an outer wall of the wide conductive line and an upper surface of the substrate is substantially equal to a second angle between the side wall of the plurality of narrow openings and the upper surface of the substrate.   
     
     
         13 . The method as claimed in  claim 11 , wherein:
 the wide opening is formed by removing a line-shaped insulating spacer pattern between the plurality of narrow openings, and   the third width of the wide opening is determined by the number of removed insulating spacer patterns.   
     
     
         14 . The method as claimed in  claim 13 , wherein the insulating spacer pattern has a tapered shape that widens towards the substrate. 
     
     
         15 . The method as claimed in  claim 13 , wherein the third width of the wide opening is at least twice the fourth width of each of the plurality of narrow openings. 
     
     
         16 . A method of forming a pattern of a semiconductor device, the method comprising:
 forming an insulating film on a substrate;   forming a lower mask layer on the insulating film;   forming a line-shaped hard mask pattern having an opening on the lower mask layer;   forming line-shaped spacers on sidewalls of the opening of the line-shaped hard mask pattern;   forming a composite mask pattern composed of the spacer and a pattern having a first width of the line-shaped hard mask patterns by removing a pattern having a second width among the line-shaped hard mask patterns, the second width being smaller than the first width;   forming a lower mask pattern by etching the lower mask layer using the composite mask pattern as an etch mask;   forming a line-shaped insulating pattern having a plurality of narrow openings by etching the insulating film using the lower mask pattern as an etching mask;   forming a wide opening between the plurality of narrow openings by removing a pattern having a third width among the line-shaped insulating patterns;   forming a conductive material layer filling the plurality of narrow openings and the wide opening of the line-shaped insulating pattern; and   polishing the conductive material layer into a conductive line having a bent portion at a location of the wide opening.   
     
     
         17 . The method as claimed in  claim 16 , wherein the conductive line includes:
 a pair of line patterns in the plurality of narrow openings; and   a bridge pattern in the wide opening, extending perpendicularly to an extension direction of the pair of line patterns, and electrically connecting the pair of line patterns.   
     
     
         18 . The method as claimed in  claim 17 , wherein:
 the conductive line has a tapered shape that narrows in width towards the substrate, and   a first angle between outer walls of the pair of line patterns and an upper surface of the substrate is substantially equal to a second angle between outer walls of the bridge pattern and the upper surface of the substrate.   
     
     
         19 . The method as claimed in  claim 17 , wherein the bridge pattern contacts one end of one of the pair of line patterns and contacts another end of the other one of the pair of line patterns. 
     
     
         20 . The method as claimed in  claim 16 , wherein:
 the wide opening is formed by removing an insulating spacer pattern between the plurality of narrow openings, and   the third width of the wide opening is determined by the number of removed insulating spacer patterns.