Semiconductor memory device

Abstract

A semiconductor memory device comprising a substrate including a cell array area and an extension area, a mold structure including, a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate, and a plurality of mold insulating films stacked alternately with the plurality of gate electrodes, a plurality of channel structures on the cell array area of the substrate, wherein each of the plurality of channel structures extends through the mold structure and intersects the plurality of gate electrodes, a plurality of cell contacts on the extension area of the substrate and respectively connected to the plurality of gate electrodes, a first interlayer insulating film on the mold structure so as to cover the plurality of channel structures and the plurality of cell contacts.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a substrate including a cell array area and an extension area;   a mold structure including:
 a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate; and 
 a plurality of mold insulating films stacked alternately with the plurality of gate electrodes; 
   a plurality of channel structures on the cell array area of the substrate, wherein each of the plurality of channel structures extends through the mold structure and intersects the plurality of gate electrodes;   a plurality of cell contacts on the extension area of the substrate and respectively connected to the plurality of gate electrodes;   a first interlayer insulating film on the mold structure and covering the plurality of channel structures and the plurality of cell contacts;   a second interlayer insulating film on the first interlayer insulating film;   a plurality of first metal patterns respectively connected to the plurality of channel structures and in the first interlayer insulating film;   a plurality of second metal patterns respectively connected to the plurality of cell contacts, an upper surface of each of the plurality of second metal patterns being coplanar with as an upper surface of each of the plurality of first metal patterns;   a first blocking pattern entirely covering the upper surfaces of the plurality of first metal patterns; and   a plurality of second blocking patterns entirely covering upper surfaces of the plurality of second metal patterns, respectively,   wherein at least a portion of the second interlayer insulating film is between adjacent ones of the plurality of second blocking patterns.   
     
     
         2 . The semiconductor memory device as claimed in  claim 1 , wherein the first blocking pattern overlaps an entirety of a portion of the substrate in the cell array area in a thickness direction of the substrate. 
     
     
         3 . The semiconductor memory device as claimed in  claim 1 , wherein a width of an upper surface of each of the plurality of second blocking patterns is greater than a width of the upper surface of each of the plurality of second metal patterns. 
     
     
         4 . The semiconductor memory device as claimed in  claim 1 , wherein a width of an upper surface of each of the plurality of second blocking patterns is equal to a width of the upper surface of each of the plurality of second metal patterns. 
     
     
         5 . The semiconductor memory device as claimed in  claim 1 , wherein the first blocking pattern includes a plurality of sub-blocking patterns respectively corresponding to the plurality of first metal patterns. 
     
     
         6 . The semiconductor memory device as claimed in  claim 5 , wherein a width of an upper surface of each of the plurality of sub-blocking patterns is greater than a width of the upper surface of each of the plurality of first metal patterns. 
     
     
         7 . The semiconductor memory device as claimed in  claim 5 , wherein at least a portion of the second interlayer insulating film is between adjacent ones of the plurality of sub-blocking patterns. 
     
     
         8 . The semiconductor memory device as claimed in  claim 1 , further comprising:
 a plurality of third metal patterns in the second interlayer insulating film;   a plurality of vias respectively on bottom surfaces of the plurality of third metal patterns;   a plurality of third blocking patterns entirely covering upper surfaces of the plurality of third metal patterns, respectively; and   a third interlayer insulating film on the second interlayer insulating film,   wherein at least a portion of the third interlayer insulating film is between adjacent ones of the plurality of third blocking patterns.   
     
     
         9 . The semiconductor memory device as claimed in  claim 8 , wherein the plurality of vias are respectively connected to the plurality of first metal patterns and the plurality of second metal patterns. 
     
     
         10 . The semiconductor memory device as claimed in  claim 8 , wherein a width of an upper surface of each of the plurality of third blocking patterns is greater than a width of a upper surface of each of the plurality of third metal patterns. 
     
     
         11 . The semiconductor memory device as claimed in  claim 8 , wherein a width of an upper surface of each of the plurality of third blocking patterns is equal to a width of an upper surface of each of the plurality of third metal patterns. 
     
     
         12 . A semiconductor memory device, comprising:
 a substrate including a cell array area, an extension area, and a pad area;   a mold structure including:
 a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate; and 
 a plurality of mold insulating films stacked alternately with the plurality of gate electrodes; 
   a plurality of channel structures on the cell array area of the substrate, wherein each of the plurality of channel structures extends through the mold structure and intersects the plurality of gate electrodes;   a plurality of cell contacts on the extension area of the substrate and respectively connected to the plurality of gate electrodes;   a plurality of first metal patterns respectively connected to the plurality of channel structures;   a first interlayer insulating film on the mold structure and covering the plurality of channel structures and the plurality of cell contacts;   a plurality of second metal patterns respectively connected to the plurality of cell contacts, an upper surface of each of the plurality of second metal patterns being coplanar with a upper surface of each of the plurality of first metal patterns; and   a first blocking layer extending along the upper surfaces of the plurality of first metal patterns and the upper surfaces of the plurality of second metal patterns, the first blocking layer having a plurality of first trenches defined therein exposing at least a portion of the first interlayer insulating film,   the first blocking layer overlapping an entirety of each of the upper surfaces of the plurality of first metal patterns, and an entirety of each of the upper surfaces of the plurality of second metal patterns in a thickness direction of the substrate.   
     
     
         13 . The semiconductor memory device as claimed in  claim 12 , wherein the plurality of first trenches are on the extension area and the pad area of the substrate, and are absent on the cell array area of the substrate. 
     
     
         14 . The semiconductor memory device as claimed in  claim 12 , wherein the plurality of first trenches non-overlap the plurality of first metal patterns and the plurality of second metal patterns in the thickness direction of the substrate. 
     
     
         15 . The semiconductor memory device as claimed in  claim 12 , further comprising a second interlayer insulating film on the first interlayer insulating film,
 wherein the second interlayer insulating film includes a first portion on the first blocking layer, and a second portion in the plurality of first trenches.   
     
     
         16 . The semiconductor memory device as claimed in  claim 12 , wherein a shape in a plan view of each of the plurality of first trenches includes a circle, a rectangle, or an ellipse. 
     
     
         17 . The semiconductor memory device as claimed in  claim 12 , further comprising:
 a second interlayer insulating film on the first interlayer insulating film;   a third interlayer insulating film on the second interlayer insulating film;   a plurality of third metal patterns in the second interlayer insulating film;   a plurality of vias respectively on bottom surfaces of the plurality of third metal patterns; and   a second blocking layer extending along upper surfaces of the plurality of third metal patterns and having a plurality of second trenches defined therein exposing at least a portion of the second interlayer insulating film,   wherein the third interlayer insulating film includes a first portion on the second blocking layer, and a second portion in the plurality of second trenches.   
     
     
         18 . The semiconductor memory device as claimed in  claim 17 , wherein some of the plurality of first trenches overlaps some of the plurality of second trenches. 
     
     
         19 . The semiconductor memory device as claimed in  claim 17 , wherein some of the plurality of first trenches overlaps each of the plurality of third metal patterns. 
     
     
         20 . A semiconductor memory device, comprising:
 a peripheral circuit structure including a peripheral circuit element; and   a cell structure on the peripheral circuit structure,   wherein the cell structure includes:   a substrate including a cell array area, an extension area, and a pad area;   a mold structure, the mold structure including:
 a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate; and 
 a plurality of mold insulating films stacked alternately with the plurality of gate electrodes; 
   a first interlayer insulating film covering the mold structure;   a plurality of channel structures on the cell array area of the substrate, each of the plurality of channel structures extending through the first interlayer insulating film and the mold structure and intersecting the plurality of gate electrodes;   a plurality of cell contacts on the extension area of the substrate, the plurality of cell contacts extending through the first interlayer insulating film and being respectively connected to the plurality of gate electrodes;   a through-contact on the pad area of the substrate, the through-contact extending through the first interlayer insulating film and being connected to the peripheral circuit element;   a plurality of first metal patterns respectively connected to the plurality of channel structures;   a plurality of second metal patterns respectively connected to the plurality of cell contacts;   a third metal pattern connected to the through-contact;   a first blocking layer extending along upper surfaces of the plurality of first metal patterns, upper surfaces of the plurality of second metal patterns, and a upper surface of the third metal pattern, the first blocking layer having a plurality of first trenches defined therein exposing at least a portion of the first interlayer insulating film;   a second interlayer insulating film on the first interlayer insulating film;   a plurality of fourth metal patterns in the second interlayer insulating film; and   a second blocking layer extending along upper surfaces of the plurality of fourth metal patterns and having a plurality of second trenches defined therein exposing at least a portion of the second interlayer insulating film,   wherein the upper surfaces of the plurality of first metal patterns, the upper surfaces of the plurality of second metal patterns, and the upper surface of the third metal pattern are coplanar with each other,   wherein the first blocking layer covers an entirety of each of the upper surfaces of the plurality of first metal patterns, an entirety of each of the upper surfaces of the plurality of second metal patterns, and an entirety of the upper surface of the third metal pattern,   wherein the second blocking layer covers an entirety of each of the upper surfaces of the plurality of fourth metal patterns;   wherein an oxide insulating material is in the plurality of first trenches and the plurality of second trenches,   wherein the plurality of first trenches is on the extension area of the substrate and the pad area, and is absent on the cell array area of the substrate.