Chip package structures, manufacturing methods thereof and electronic devices

Abstract

In one example, the disclosed semiconductor structure includes a package substrate, a first chip, a conductive pillar and a second chip, wherein the package substrate has a first surface; the first chip is located on the first surface of the package substrate and electrically connected to the package substrate; the conductive pillar is located on the first surface of the package substrate and electrically connected to the package substrate; the second chip is located on a side of the first chip and the conductive pillar away from the package substrate and electrically connected to the conductive pillar; and an orthographic projection of the conductive pillar on the package substrate is located within a range of an orthographic projection of the first chip or the second chip on the package substrate. The chip package structure is configured for connection with a circuit board in the electronic device. Other examples are disclosed.

What is claimed is: 
     
         1 . A chip package structure comprising:
 a package substrate having a first surface;   a first chip located on the first surface of the package substrate and electrically connected to the package substrate;   a conductive pillar located on the first surface of the package substrate and electrically connected to the package substrate; and   a second chip located on a side of the first chip and the conductive pillar away from the package substrate and electrically connected to the conductive pillar, an orthographic projection of the conductive pillar on the package substrate being located within a range of an orthographic projection of the first chip or the second chip on the package substrate.   
     
     
         2 . The chip package structure according to  claim 1 , wherein the chip package structure further includes a package layer, wherein
 the package layer is located between the package substrate and the second chip, and covers the first chip and surrounds sides of the conductive pillar.   
     
     
         3 . The chip package structure according to  claim 2 , wherein an orthographic projection of the second chip on the package substrate is located within a range of an orthographic projection of the package layer on the package substrate. 
     
     
         4 . The chip package structure according to  claim 2 , wherein the chip package structure further includes a first filling portion, wherein
 at least part of the first filling portion is located between the package layer and the second chip and the first filling portion surrounds each pin of the second chip.   
     
     
         5 . The chip package structure according to  claim 2 , wherein the chip package structure further includes an electromagnetic shielding layer, wherein
 the electromagnetic shielding layer at least covers the second chip as well as sides of the package layer.   
     
     
         6 . The chip package structure according to  claim 5 , wherein the package substrate includes at least one ground wire; and
 the electromagnetic shielding layer also covers sides of the package substrate and is electrically connected to the ground wire.   
     
     
         7 . The chip package structure according to  claim 1  wherein the second chip includes a plurality of sub-chips sequentially stacked in a direction perpendicular to and away from the package substrate. 
     
     
         8 . The chip package structure according to  claim 7 , wherein two adjacent sub-chips are electrically connected to each other. 
     
     
         9 . The chip package structure according to  claim 7 , wherein one of the plurality of sub-chips close to the package substrate is electrically connected to the conductive pillar, and others of the plurality of sub-chips are electrically connected to the package substrate by a wire. 
     
     
         10 . The chip package structure according to  claim 1 , wherein a surface on a side of the second chip close to the package substrate is higher than a surface on a side of the first chip away from the package substrate, with respect to the first surface of the package substrate. 
     
     
         11 . The chip package structure according to  claim 10 , wherein a distance between the surface on the side of the second chip close to the package substrate and the first surface of the package substrate is h 1 , a distance between the surface on the side of the first chip away from the package substrate and the first surface of the package substrate is h 2 , and h 1  and h 2  meet the following condition: 
       
         
           
             
               
                 5 
                 8 
               
               ≤ 
               
                 
                   h 
                   ⁢ 
                   2 
                 
                 
                   h 
                   ⁢ 
                   1 
                 
               
               ≤ 
               
                 
                   4 
                   5 
                 
                 . 
               
             
           
         
       
     
     
         12 . The chip package structure according to  claim 1 , wherein a number of the conductive pillars is greater than one, and a plurality of conductive pillars are at least located on two opposite sides of the first chip. 
     
     
         13 . The chip package structure according to  claim 1 , wherein the chip package structure further includes a second filling portion, wherein
 at least part of the second filling portion is located between the package substrate and the first chip and the second filling portion surrounds each pin of the first chip.   
     
     
         14 . The chip package structure according to  claim 1 , wherein the package substrate has a second surface opposite to the first surface; and
 the chip package structure further includes a solder ball located on the second surface of the package surface and electrically connected to the package substrate.   
     
     
         15 . A chip package structure comprising:
 a package substrate having a first surface;   a first chip disposed on the first surface of the package substrate and electrically connected to the package substrate; and   a second chipset located on a side of the first chip away from the package substrate, electrically connected to the package substrate, and comprising a plurality of second chips sequentially stacked in a direction perpendicular to and away from the package substrate.   
     
     
         16 . The chip package structure according to  claim 15 , wherein two adjacent second chips are electrically connected to each other. 
     
     
         17 . The chip package structure according to  claim 15 , wherein the chip package structure further includes a package layer, wherein
 the package layer is located between the package substrate and the second chipset and covers the first chip.   
     
     
         18 . The chip package structure according to  claim 17 , wherein the chip package structure further includes an electromagnetic shielding layer, wherein
 the electromagnetic shielding layer at least covers the second chipset as well as sides of the package layer.   
     
     
         19 . The chip package structure according to  claim 15 , wherein a surface on a side of the second chipset close to the package substrate is higher than a surface on a side of the first chip away from the package substrate, with respect to the first surface of the package substrate. 
     
     
         20 . A manufacturing method of a chip package structure, the method comprising:
 providing a package substrate having a first surface;   forming a conductive pillar on the first surface of the package substrate, the conductive pillar being electrically connected to the package substrate;   disposing a first chip on the first surface of the package substrate, the first chip being electrically connected to the package substrate; and   disposing a second chip on a side of the conductive pillar and the first chip away from the package substrate, the second chip being electrically connected to the conductive pillar, an orthographic projection of the conductive pillar on the package substrate being located within a range of an orthographic projection of the first chip or the second chip on the package substrate.