Apparatuses and methods including circuits in gap regions of a memory array

Abstract

Apparatuses and methods including circuits in gap regions of a memory array are disclosed. An example apparatus includes first and second memory mats adjacent along a first direction, and further includes a region between the first and second memory mats along the first direction. The region includes a local input/output (LIO) line that extends along a second direction perpendicular to the first direction through the region, and further includes a LIO driver and a LIO precharge circuit coupled to the LIO line. The LIO driver is configured to drive the LIO line to data voltage levels based on data read from memory cells or based on data to be written to memory cells, and the LIO precharge circuit is configured to provide a LIO precharge voltage to the LIO lines.

What is claimed is: 
     
         1 . An apparatus, comprising:
 first and second memory mats;   sense amplifiers included in a first gap region between the first and second memory mats;   a local input/output (LIO) line included in the first gap region;   a LIO driver and a LIO precharge circuit coupled to the LIO line and included in the first gap region; and   an activation voltage driver circuit included in a second gap region, the second gap region including a boundary shared with the first gap region, and including a first corner at a corner of the first memory mat and further including a second corner at a corner of the second memory mat, the activation voltage driver circuit configured to provide an activation voltage to the sense amplifiers.   
     
     
         2 . The apparatus of  claim 1 , wherein the LIO driver and the LIO precharge circuit are included in a read-write gap region of the first gap region, and wherein the sense amplifiers are included in a sense amplifier region of the first gap region. 
     
     
         3 . The apparatus of  claim 1 , further comprising a second activation voltage driver included in the first gap region, the second activation voltage driver configured to provide a second activation voltage to the sense amplifiers. 
     
     
         4 . The apparatus of  claim 1 , further comprising:
 third and fourth memory mats;   second sense amplifiers in a third gap region between the third and fourth memory mats;   a second LIO line included in the third gap region; and   a second LIO driver and a second LIO precharge circuit coupled to the second LIO line and included in the third gap region,   wherein the activation voltage driver circuit is configured to provide the activation voltage to the second sense amplifiers, and the second gap region includes a second boundary shared with the third gap region, and includes a third corner at a corner of the third memory mat and further includes a fourth corner at a corner of the fourth memory mat.   
     
     
         5 . The apparatus of  claim 4 , further comprising a conductive activation voltage mesh coupled to the activation voltage driver circuit and coupled to the sense amplifiers and second sense amplifiers to provide the activation voltage thereto. 
     
     
         6 . The apparatus of  claim 5 , wherein the conductive activation voltage mesh includes conductive lines in the first and third gap regions, the conductive lines including first conductive lines from a first metal layer and second conductive lines from a second metal layer. 
     
     
         7 . The apparatus of  claim 6 , wherein the conductive lines of the conductive activation voltage mesh further includes third conductive lines from a third metal layer. 
     
     
         8 . An apparatus, comprising:
 first and second memory mats adjacent along a first direction, the first and second memory mats including memory cells;   a region between the first and second memory mats along the first direction, the region including a local input/output (LIO) line that extends along a second direction perpendicular to the first direction through the region, and further including a LIO driver and a LIO precharge circuit coupled to the LIO line, the LIO driver configured to drive the LIO line to data voltage levels based on data read from the memory cells or based on data to be written to the memory cells, and the LIO precharge circuit configured to provide a LIO precharge voltage to the LIO lines.   
     
     
         9 . The apparatus of  claim 8 , further comprising a second region adjacent the region in the second direction, the second region including a first activation voltage driver circuit configured to provide a first activation voltage to sense amplifiers included in the region between the first and second memory mats along the first direction. 
     
     
         10 . The apparatus of  claim 9 , wherein the region between the first and second memory mats along the first direction includes a second activation voltage driver circuit, the second activation voltage driver circuit configured to provide a second activation voltage different than the first activation voltage to the sense amplifiers included in the region between the first and second memory mats along the first direction. 
     
     
         11 . The apparatus of  claim 9 , wherein the second region further includes a second activation voltage driver circuit, the second activation voltage driver circuit configured to provide the first activation voltage to the sense amplifiers included in the region between the first and second memory mats along the first direction, the second activation voltage driver circuit having a different current drive than the first activation voltage driver circuit. 
     
     
         12 . The apparatus of  claim 8 , further comprising a conductive activation voltage mesh including conductive lines that extend in the second direction in the region, the conductive activation voltage mesh configured to provide an activation voltage to circuits included in the region. 
     
     
         13 . The apparatus of  claim 12 , wherein the conductive lines of the conductive activation voltage mesh comprises first and second conductive lines that extend in the second direction in the region, and at least a portion of a sense amplifier region including sense amplifiers is between the first and second conductive lines. 
     
     
         14 . The apparatus of  claim 13 , wherein the first conductive line is from a first conductive layer and the second conductive line is from a different conductive layer than the first conductive layer. 
     
     
         15 . The apparatus of  claim 12 , wherein the conductive lines of the conductive activation voltage mesh comprises first and second conductive lines that extend in the second direction in the region, and at least a portion of a read-write gap region including the LIO driver and the LIO precharge circuit is between the first and second conductive lines. 
     
     
         16 . The apparatus of  claim 15 , wherein the conductive activation voltage mesh further includes conductive lines in the region coupled to first and second conductive lines and extend across the read-write gap region along the first direction. 
     
     
         17 . An apparatus, comprising:
 first and second memory mats adjacent along a first direction, the first and second memory mats including memory cells;   a first region between the first and second memory mats and including sense amplifiers coupled to the memory cells, and further including a local/input output (LIO) line, a LIO driver, and a LIO precharge circuit;   a second region adjacent the first region and including activation voltage driver circuits configured to provide an activation voltage; and   a conductive activation voltage mesh coupled to the activation voltage driver circuit and the sense amplifiers to provide the activation voltage from the activation voltage driver circuit in the second region to the sense amplifiers in the first region.   
     
     
         18 . The apparatus of  claim 17 , wherein the first region comprises a read-write gap region including the LIO driver and the LIO precharge circuit, and the read-write gap region has at least a portion that is between first and second conductive lines of the conductive activation voltage mesh that extend in the first region. 
     
     
         19 . The apparatus of  claim 18 , wherein the first region further comprises a sense amplifier region including the sense amplifiers and the sense amplifier region has at least a portion that is between the first conductive line and a third conductive line of the conductive activation voltage mesh that extends in the first region. 
     
     
         20 . The apparatus of  claim 18 , wherein the first region further comprises a first sense amplifier region including a first portion of the sense amplifiers and a second sense amplifier region including a second portion of the sense amplifiers, the read-write gap region between the first and second sense amplifier regions. 
     
     
         21 . The apparatus of  claim 17 , further comprising a second activation voltage driver included in the second region that is coupled to conductive activation voltage mesh, the second activation voltage driver configured to provide the activation voltage with a current drive different than the activation voltage driver.