Ferroelectric memory and forming method thereof, and electronic device

Abstract

A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a transistor and a plurality of ferroelectric capacitors. In other words, each memory cell includes at least two ferroelectric capacitors to implement multi-bit data storage. The transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate. Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer. The first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction.

What is claimed is: 
     
         1 . A ferroelectric memory, comprising:
 a substrate; and   a plurality of memory cells, formed on the substrate, wherein   each memory cell comprises a transistor and a plurality of ferroelectric capacitors;   the transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate;   each of the plurality of ferroelectric capacitor comprises a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer;   the first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction; and   the shared first electrode layer is electrically connected to the transistor.   
     
     
         2 . The ferroelectric memory according to  claim 1 , wherein the ferroelectric memory further comprises a plate line layer, wherein the plate line layer is located on a first plane parallel to the substrate; and
 the plurality of second electrode layers of the plurality of ferroelectric capacitors located on the first plane are interconnected through the plate line layer.   
     
     
         3 . The ferroelectric memory according to  claim 1 , wherein the transistor and the plurality of ferroelectric capacitors are all manufactured through a back-end-of-line process. 
     
     
         4 . The ferroelectric memory according to  claim 1 , wherein the transistor comprises a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer, wherein
 the first electrode and the second electrode are arranged in the first direction, the gate is a vertical structure that extends in the first direction, one of two opposite sides of the gate in a second direction has the semiconductor layer, the semiconductor layer is electrically connected to the first electrode and the second electrode, the gate and the semiconductor layer are isolated by the gate dielectric layer, and the second direction is a direction parallel to the substrate.   
     
     
         5 . The ferroelectric memory according to  claim 4 , wherein the semiconductor layer is a vertical structure that extends in the first direction, one of two opposite ends of the semiconductor layer in the first direction is in contact with the first electrode, and the other end is in contact with the second electrode. 
     
     
         6 . The ferroelectric memory according to  claim 5 , wherein a surface opposite to the second electrode in the first electrode is a first wall surface, and a surface opposite to the first electrode in the second electrode is a second wall surface; and
 the one of the opposite two ends of the semiconductor layer in the first direction is in contact with the first wall surface, and the other end is in contact with the second wall surface.   
     
     
         7 . The ferroelectric memory according to  claim 5 , wherein a surface opposite to the second electrode in the first electrode is a first wall surface, and a surface that is in the first electrode and that is adjacent to the first wall surface is a first side surface;
 a surface opposite to the first electrode in the second electrode is a second wall surface, a surface that is in the second electrode and that is adjacent to the second wall surface is a second side surface, and the first side surface and the second side surface are located on a same side; and   the one of the opposite two ends of the semiconductor layer in the first direction is in contact with the first side surface, and the other end is in contact with the second side surface.   
     
     
         8 . The ferroelectric memory according to  claim 4 , wherein the semiconductor layer comprises a first part and a second part both of which extend in the second direction, and a third part that extends in the first direction and that is connected to both the first part and the second part;
 a surface opposite to the second electrode in the first electrode is a first wall surface, and a surface opposite to the first electrode in the second electrode is a second wall surface; and   the first part is disposed on the first wall surface, and the second part is disposed on the second wall surface.   
     
     
         9 . The ferroelectric memory according to  claim 4 , wherein the semiconductor layer comprises a first part that extends in the second direction, and a third part that extends in the first direction and that is connected to the first part;
 a surface opposite to the second electrode in the first electrode is a first wall surface, and a surface opposite to the first electrode in the second electrode is a second wall surface;   the ferroelectric memory further comprises a connection electrode, and the connection electrode is disposed on the second wall surface; and   the third part is in contact with the first wall surface, and the first part is in contact with the connection electrode.   
     
     
         10 . The ferroelectric memory according to  claim 4 , wherein the surface opposite to the second electrode in the first electrode is the first wall surface, and the surface opposite to the first electrode in the second electrode is the second wall surface; and
 the gate is located in a region between the first wall surface and the second wall surface.   
     
     
         11 . The ferroelectric memory according to  claim 4 , wherein the surface opposite to the second electrode in the first electrode is the first wall surface, and the surface that is in the first electrode and that is adjacent to the first wall surface is the first side surface;
 the surface opposite to the first electrode in the second electrode is the second wall surface, the surface that is in the second electrode and that is adjacent to the second wall surface is the second side surface, and the first side surface and the second side surface are located on a same side; and   the gate is located on the side on which the first side surface and the second side surface are located.   
     
     
         12 . The ferroelectric memory according to  claim 1 , wherein the transistor is manufactured through a gate-all-around GAA process. 
     
     
         13 . The ferroelectric memory according to  claim 1 , wherein the transistor is manufactured through a channel-all-around CAA process. 
     
     
         14 . The ferroelectric memory according to  claim 13 , wherein the transistor comprises a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer, wherein
 the first electrode and the second electrode are arranged in the first direction, the gate is a vertical structure that extends in the first direction, the semiconductor layer surrounds the outside of the gate, the semiconductor layer and the gate are isolated by the gate dielectric layer, the first electrode surrounds the periphery of the semiconductor layer and is electrically connected to the semiconductor layer, and the semiconductor layer is electrically connected to the second electrode.   
     
     
         15 . The ferroelectric memory according to  claim 1 , wherein the ferroelectric memory further comprises:
 a bit line, a word line, and a plate line, wherein   the gate of the transistor is electrically connected to the word line;   the first electrode of the transistor is electrically connected to the bit line;   the second electrode of the transistor is electrically connected to the shared first electrode layer; and   the second electrode layer of the ferroelectric capacitor is electrically connected to the plate line.   
     
     
         16 . The ferroelectric memory according to  claim 15 , wherein the plurality of memory cells form a first memory array layer and a second memory array layer that are arranged in the first direction;
 the transistor in the first memory array layer is disposed away from the substrate relative to the plurality of ferroelectric capacitors; and   the transistor in the second memory array layer is disposed close to the substrate relative to the plurality of ferroelectric capacitors.   
     
     
         17 . A ferroelectric memory, comprising:
 a word line, a bit line, a plate line; and   a plurality of memory cells, wherein each of the memory cells comprises:   a transistor and a plurality of ferroelectric capacitors, wherein   any ferroelectric capacitor comprises a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer, and the transistor comprises a first electrode, a second electrode, and a gate; and   the first electrode of the transistor is electrically connected to the bit line, the second electrode of the transistor is electrically connected to the plurality of first electrode layers of the plurality of ferroelectric capacitors, the gate of the transistor is electrically connected to the word line, and the second electrode layer of the ferroelectric capacitor is electrically connected to the plate line.   
     
     
         18 . The ferroelectric memory according to  claim 17 , wherein
 in a write stage, the word line is configured to receive a first word line electrical control signal, so that the transistor is turned on, the bit line is configured to receive a first bit line control signal, the plate line electrically connected to a selected ferroelectric capacitor is configured to receive a first plate line control signal, and a voltage difference between the first bit line control signal and the first plate line control signal enables polarization of the ferroelectric layer of the selected ferroelectric capacitor.   
     
     
         19 . The ferroelectric memory according to  claim 17 , wherein
 in a first read stage, the word line is configured to receive the first word line electrical control signal, so that the transistor is turned on, and the bit line is configured to receive a second bit line control signal, to perform voltage pre-charging on the first electrode layer of the selected ferroelectric capacitor;   in a second read stage, the word line is configured to receive a second word line electrical control signal, so that the transistor is turned off, the plate line electrically connected to the selected ferroelectric capacitor is configured to receive a second plate line control signal, and a voltage difference between the second plate line control signal and the first electrode layer keeps a polarization direction of the ferroelectric layer of the selected ferroelectric capacitor unchanged, or reverses the polarization direction of the ferroelectric layer of the selected ferroelectric capacitor; and   
       in a third read stage, the word line is configured to receive the first word line electrical control signal, so that the transistor is turned on, and a voltage or a current on the bit line is detected to read information stored by the selected ferroelectric capacitor. 
     
     
         20 . A method of forming of a ferroelectric memory, comprising:
 forming a transistor on a substrate; and   forming a plurality of ferroelectric capacitors, wherein the transistor and the plurality of ferroelectric capacitors form a memory cell, the transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate, each of the plurality of ferroelectric capacitors comprises a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer, the first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction, and the shared first electrode layer is electrically connected to the transistor.