Chip package structure and manufacturing method thereof

Abstract

A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.

What is claimed is: 
     
         1 . A chip package structure, comprising:
 a heat dissipation base;   a first redistribution layer;   a second redistribution layer disposed on the heat dissipation base and thermally coupled to the heat dissipation base, and the second redistribution layer is located between the first redistribution layer and the heat dissipation base;   a plurality of chips disposed between the second redistribution layer and the first redistribution layer and having different thicknesses, wherein each of the chips has an active surface facing the first redistribution layer and an inactive surface facing the second redistribution layer, and the active surfaces of the chips are electrically connected to the second redistribution layer;   a plurality of metal stacks disposed between the second redistribution layer and the inactive surfaces of the chips, wherein the inactive surfaces of the chips are thermally coupled to the second redistribution layer via the metal stacks, and the metal stacks have different thicknesses;   a plurality of conductive structures disposed between the second redistribution layer and the first redistribution layer and electrically connected to the second redistribution layer and the first redistribution layer, wherein each of the conductive structures comprises a metal inner core and a metal outer layer covering the metal inner core, and the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer; and   an encapsulant filled between the second redistribution layer and the first redistribution layer.   
     
     
         2 . The chip package structure of  claim 1 , wherein each of the metal stacks comprises a first metal layer and a second metal layer, the first metal layer is located between the second redistribution layer and the second metal layer, and the second metal layer is located between the first metal layer and the inactive surface of the corresponding chip. 
     
     
         3 . The chip package structure of  claim 2 , wherein the first metal layers of the metal stacks have different thicknesses. 
     
     
         4 . The chip package structure of  claim 3 , wherein a thickness of the first metal layer of one of the metal stacks connected to one of the thicker chips is less than a thickness of the first metal layer of another metal stack connected to another thinner chip. 
     
     
         5 . The chip package structure of  claim 3 , wherein a total thickness of one of the chips and one of the metal stacks connected to each other is equal to a total thickness of another chip and another metal stack connected to each other. 
     
     
         6 . The chip package structure of  claim 2 , wherein the second metal layers of the metal stacks have a same thickness. 
     
     
         7 . The chip package structure of  claim 2 , wherein a material of the first metal layer of each of the metal stacks comprises copper, and a material of the second metal layer comprises tin. 
     
     
         8 . The chip package structure of  claim 1 , wherein the metal outer layer of each of the conductive structures has a first contact surface in contact with the second redistribution layer, the metal inner core has a second contact surface exposed to the first contact surface, and the second contact surface is in contact with the second redistribution layer. 
     
     
         9 . The chip package structure of  claim 8 , wherein the first contact surface of the metal outer layer of each of the conductive structures and the second contact surface of the metal inner core are coplanar. 
     
     
         10 . The chip package structure of  claim 8 , wherein the first contact surface of the metal outer layer of each of the conductive structures surrounds the second contact surface of the metal inner core. 
     
     
         11 . The chip package structure of  claim 1 , wherein the metal outer layer of each of the conductive structures is in contact with the first redistribution layer, and the metal inner core and the first redistribution layer are separated by the metal outer layer. 
     
     
         12 . The chip package structure of  claim 1 , wherein each of the conductive structures is a conductive ball or a conductive pillar. 
     
     
         13 . The chip package structure of  claim 1 , wherein a material of the metal inner core of each of the conductive structures is copper, and a material of the metal outer layer is tin. 
     
     
         14 . The chip package structure of  claim 1 , wherein a material of the heat dissipation base comprises copper or silicon. 
     
     
         15 . The chip package structure of  claim 1 , further comprising:
 a plurality of underfill layers respectively disposed between the active surfaces of the chips and the first redistribution layer.   
     
     
         16 . The chip package structure of  claim 15 , wherein each of the chips also has a side surface connected to the active surface, and the underfill layer further covers the side surface of the chip and covers the metal stack. 
     
     
         17 . The chip package structure of  claim 1 , further comprising a third redistribution layer, wherein the third redistribution layer is disposed on the first redistribution layer, and the first redistribution layer is located between the encapsulant and the third redistribution layer. 
     
     
         18 . The chip package structure of  claim 17 , wherein the third redistribution layer comprises a molding layer covering the first redistribution layer, at least two circuits disposed on the molding layer, and at least two conductive vias penetrating through the molding layer, and the two circuits are respectively electrically connected to the first redistribution layer via the two conductive vias. 
     
     
         19 . The chip package structure of  claim 17 , wherein the third redistribution layer comprises a first molding layer covering the first redistribution layer, a second molding layer disposed above the first molding layer, a dielectric layer and a first circuit disposed between the first molding layer and the second molding layer, a second circuit and a third circuit disposed on the second molding layer, a first conductive via, a second conductive via, and a third conductive via, the first conductive via penetrates through the first molding layer, and the first circuit is electrically connected to the first redistribution layer via the first conductive via, the second conductive via and the third conductive via penetrate through the second molding layer, the dielectric layer, and the first molding layer, and the second circuit and the third circuit are electrically connected to the first redistribution layer via the second conductive via and the third conductive via respectively. 
     
     
         20 . The chip package structure of  claim 17 , wherein the third redistribution layer comprises a molding layer disposed above the first redistribution layer, at least two circuits disposed at a side of the molding layer, at least two conductive vias penetrating through the molding layer, and at least two conductive pads and at least two conductive balls disposed at another side of the molding layer, and the two conductive balls are located between the first redistribution layer and the two conductive pads, and each of the circuits is electrically connected to the first redistribution layer via one of the conductive vias, one of the conductive pads, and one of the conductive balls. 
     
     
         21 . The chip package structure of  claim 1 , wherein the heat dissipation base comprises a plurality of heat dissipation portions and a plurality of electrical transmission portions, the heat dissipation portions are respectively located opposite to the chips and thermally coupled to the second redistribution layer, and the electrical transmission portions are located in a periphery of the heat dissipation portions, wherein the electrical transmission portions are respectively located opposite to the conductive structures and electrically connected to the second redistribution layer. 
     
     
         22 . The chip package structure of  claim 1 , wherein each of the metal stacks comprises a metal layer and a sintered material layer, wherein the metal layer is located between the second redistribution layer and the sintered material layer, and the sintered material layer is located between the metal layer and the inactive surface of the corresponding chip. 
     
     
         23 . A manufacturing method of a chip package structure, comprising:
 forming a plurality of metal stacks on a first carrier;   providing a plurality of chips having different sizes, wherein each of the chips has an active surface and an inactive surface opposite to the active surface, and the inactive surfaces of the chips are bonded to the metal stacks;   grinding a side of the first carrier opposite to the metal stacks, and cutting the first carrier to form a plurality of sacrificial layers bonded to the metal stacks, wherein the sacrificial layers have a same size;   forming a first redistribution layer on a second carrier;   transferring the corresponding metal stack and chip onto the first redistribution layer via each of the sacrificial layers, and bonding the active surfaces of the chips to the first redistribution layer;   forming a plurality of conductive structures on the first redistribution layer, wherein each of the conductive structures comprises a metal inner core and a metal outer layer covering the metal inner core;   forming an encapsulant on the first redistribution layer to cover the chips, the metal stacks, the sacrificial layers, and the conductive structures;   grinding a side of the encapsulant opposite to the first redistribution layer and removing the sacrificial layers, partially removing the metal stacks, and partially removing the metal inner core and the metal outer layer of each of the conductive structures, so that the metal stacks have different thicknesses, and partially exposing the metal inner core of each of the conductive structures to the metal outer layer;   forming a second redistribution layer on the encapsulant so that the metal stacks are thermally coupled to the second redistribution layer, and the metal inner core in each of the conductive structures exposed to the metal outer layer is in contact with the second redistribution layer;   removing the second carrier; and   bonding a heat dissipation base to a side of the second redistribution layer opposite to the encapsulant.   
     
     
         24 . The manufacturing method of the chip package structure of  claim 23 , wherein the chips have different thicknesses. 
     
     
         25 . The manufacturing method of the chip package structure of  claim 23 , wherein each of the sacrificial layers has a surface opposite to the corresponding metal stack, and an area of the surface is greater than an area of the inactive surface of the corresponding chip. 
     
     
         26 . The manufacturing method of the chip package structure of  claim 23 , wherein a width of each of the sacrificial layers is greater than a width of the corresponding metal stack. 
     
     
         27 . The manufacturing method of the chip package structure of  claim 23 , wherein a width of each of the sacrificial layers is greater than a width of the corresponding chip. 
     
     
         28 . The manufacturing method of the chip package structure of  claim 23 , wherein each of the metal stacks comprises a first metal layer and a second metal layer, and the second metal layer is located between the first metal layer and the inactive surface of the corresponding chip. 
     
     
         29 . The manufacturing method of the chip package structure of  claim 28 , wherein partially removing the metal stacks is grinding the first metal layers, and the first metal layers have different thicknesses after grinding. 
     
     
         30 . The manufacturing method of the chip package structure of  claim 28 , wherein the second metal layers of the metal stacks have a same thickness. 
     
     
         31 . The manufacturing method of the chip package structure of  claim 28 , wherein partially removing the metal stacks is grinding the first metal layers, and the first metal layers have different removal amounts. 
     
     
         32 . The manufacturing method of the chip package structure of  claim 31 , wherein according to the different thicknesses of the chips, the first metal layers have different removal amounts, and a removal amount of the first metal layer of one of the metal stack connected to a thicker chip is greater than a removal amount of the first metal layer of another metal stack connected to another thinner chip. 
     
     
         33 . The manufacturing method of the chip package structure of  claim 28 , wherein the metal outer layer and the metal inner core of each of the conductive structures after grinding respectively form a first contact surface and a second contact surface, and the first contact surface and the second contact surface are coplanar. 
     
     
         34 . The manufacturing method of the chip package structure of  claim 33 , wherein when forming the second redistribution layer on the encapsulant, the first contact surface of the metal outer layer of each of the conductive structures and the second contact surface of the metal inner core are in contact with the second redistribution layer. 
     
     
         35 . The manufacturing method of the chip package structure of  claim 23 , further comprising:
 forming a plurality of underfill layers between the active surfaces of the chips and the first redistribution layer after the active surfaces of the chips are bonded to the first redistribution layer.   
     
     
         36 . A chip package structure, comprising:
 a heat dissipation base;   a first redistribution layer;   a second redistribution layer disposed on the heat dissipation base and thermally coupled to the heat dissipation base, and the second redistribution layer is located between the first redistribution layer and the heat dissipation base;   a chip disposed between the second redistribution layer and the first redistribution layer, wherein the chip has an active surface facing the first redistribution layer and an inactive surface facing the second redistribution layer, and the active surface is electrically connected to the second redistribution layer;   a metal stack disposed between the second redistribution layer and the inactive surface, and the inactive surface is thermally coupled to the second redistribution layer via the metal stack;   a plurality of conductive structures disposed between the second redistribution layer and the first redistribution layer and electrically connected to the second redistribution layer and the first redistribution layer, wherein each of the conductive structures comprises a metal inner core and a metal outer layer covering the metal inner core, and the metal inner core and the metal outer layer are partially removed so that the metal inner core is partially exposed on the metal outer layer to be in contact with the second redistribution layer; and   an encapsulant filled between the second redistribution layer and the first redistribution layer.