Semiconductor package

Abstract

A semiconductor package is provided that includes: a first semiconductor die, and a second semiconductor die on the first semiconductor die. The first semiconductor die includes a semiconductor substrate, a wiring layer on an active surface of the semiconductor substrate, a redistribution pattern on an inactive surface of the semiconductor substrate, a first passivation layer on the inactive surface of the semiconductor substrate wherein the first passivation layer is on the redistribution pattern and has an opening that exposes a top surface of the redistribution pattern, and a backside pad on the first passivation layer and coupled through the opening to the redistribution pattern. An inner lateral surface of the opening is inclined at an angle of 90 to 105 degrees relative to the top surface of the redistribution pattern. A thickness of the first passivation layer is 0.3 to 0.5 times a thickness of the redistribution pattern.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a first semiconductor die; and   a second semiconductor die on the first semiconductor die,   wherein the first semiconductor die comprises:
 a semiconductor substrate; 
 a wiring layer on an active surface of the semiconductor substrate; 
 a redistribution pattern on an inactive surface of the semiconductor substrate; 
 a first passivation layer on the inactive surface of the semiconductor substrate, wherein the first passivation layer is on the redistribution pattern and has an opening that exposes a top surface of the redistribution pattern; and 
 a backside pad on the first passivation layer and coupled through the opening to the redistribution pattern, 
   wherein an inner lateral surface of the opening is inclined at an angle of 90 degrees to 105 degrees relative to the top surface of the redistribution pattern, and   wherein a thickness of the first passivation layer is 0.3 times to 0.5 times a thickness of the redistribution pattern.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the first passivation layer comprises multiple layers. 
     
     
         3 . The semiconductor package of  claim 2 , wherein the multiple layers of the first passivation layer comprise a silicon nitride layer and a silicon oxide layer. 
     
     
         4 . The semiconductor package of  claim 1 , wherein a width of the opening is in a range of 1 μm to 10 μm. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the thickness of the first passivation layer is constant on the semiconductor substrate. 
     
     
         6 . The semiconductor package of  claim 5 , wherein the thickness of the first passivation layer is in a range of 0.5 μm to 2 μm. 
     
     
         7 . The semiconductor package of  claim 1 , wherein the first semiconductor die further comprises a second passivation layer that is on the inactive surface of the semiconductor substrate,
 wherein the redistribution pattern is on the second passivation layer, and   wherein, on the second passivation layer, the first passivation layer is on the redistribution pattern.   
     
     
         8 . The semiconductor package of  claim 7 , wherein the second passivation layer comprises multiple layers. 
     
     
         9 . The semiconductor package of  claim 8 , wherein the multiple layers of the second passivation layer comprise a silicon nitride layer and a silicon oxide layer. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the second semiconductor die is mounted on the first semiconductor die by a die connection terminal on the backside pad of the first semiconductor die. 
     
     
         11 . The semiconductor package of  claim 1 , wherein the first semiconductor die further comprises a plurality of through vias that vertically penetrate the semiconductor substrate and are coupled to the redistribution pattern. 
     
     
         12 . The semiconductor package of  claim 1 , further comprising:
 a plurality of external terminals on a front surface of the first semiconductor die:   an underfill layer that fills a space between the first semiconductor die and the second semiconductor die; and   a molding layer on the first semiconductor die, wherein the molding layer surrounds the second semiconductor die in a horizontal direction of the semiconductor package.   
     
     
         13 . The semiconductor package of  claim 1 , wherein the first semiconductor die further comprises a seed layer between the backside pad and the first passivation layer,
 wherein, below the backside pad, the seed layer has an under-cut region that is recessed from a lateral surface of the backside pad.   
     
     
         14 . A semiconductor package, comprising:
 a first semiconductor die comprising:
 a semiconductor substrate: 
 a plurality of through vias that vertically penetrate the semiconductor substrate; 
 a plurality of redistribution patterns on a rear surface of the semiconductor substrate and connected to the through vias: 
 a first passivation layer on the rear surface of the semiconductor substrate and on the plurality of redistribution patterns; and 
 a plurality of pads on the first passivation layer: 
   a second semiconductor die on the first semiconductor die, wherein the second semiconductor die is mounted on the plurality of pads;   a molding layer on a rear surface of the second semiconductor die, wherein the molding layer surrounds the second semiconductor die in a horizontal direction of the semiconductor package; and   a plurality of external terminals on a front surface of the first semiconductor die,   wherein each of the plurality of pads comprises:
 a pad part on the first passivation layer; and 
 a via part that extends from a bottom surface of the pad part and penetrates the first passivation layer such as to connect with a respective one of the plurality of redistribution patterns, 
   wherein the via part has a pillar shape that has a width that is constant, and   wherein the first passivation layer comprises a silicon nitride layer and a silicon oxide layer.   
     
     
         15 . The semiconductor package of  claim 14 , wherein a thickness of the first passivation layer is 0.3 times to 0.5 times a thickness of the plurality of redistribution patterns. 
     
     
         16 . The semiconductor package of  claim 14 , wherein the width of the via part is in a range of 1 μm to 10 μm. 
     
     
         17 . The semiconductor package of  claim 14 , wherein a thickness of the first passivation layer is constant on the semiconductor substrate. 
     
     
         18 . The semiconductor package of  claim 14 , wherein the first semiconductor die further comprises a second passivation layer that is on the rear surface of the semiconductor substrate,
 wherein the plurality of redistribution patterns are on the second passivation layer, and   wherein, on the second passivation layer, the first passivation layer is on the plurality of redistribution patterns.   
     
     
         19 . The semiconductor package of  claim 18 , wherein the second passivation layer comprises a silicon nitride layer and a silicon oxide layer. 
     
     
         20 . A semiconductor package, comprising:
 a first semiconductor die; and   a second semiconductor die on the first semiconductor die,   wherein the first semiconductor die comprises:
 a semiconductor substrate: 
 a wiring layer on an active surface of the semiconductor substrate; 
 a first passivation layer on an inactive surface of the semiconductor substrate: 
 a redistribution pattern on the first passivation layer: 
 a second passivation layer on the first passivation layer, the second passivation layer on the redistribution pattern and having an opening that exposes a top surface of the redistribution pattern; and 
 a backside pad on the second passivation layer and coupled through the opening to the redistribution pattern, 
   wherein a thickness of the second passivation layer is less than a thickness of the redistribution pattern,   wherein the thickness of the second passivation layer is constant on the semiconductor substrate, and   wherein the second passivation layer comprises a silicon nitride layer and a silicon oxide layer.