Quantum circuit design apparatus, computer-readable recording medium storing quantum circuit design program, and quantum circuit design method

Abstract

A quantum circuit design apparatus includes: a memory; and a processor coupled to the memory and configured to: detect a first gate indicating a predetermined operation on a plurality of first quantum bits among a plurality of quantum bits included in a first quantum circuit, which includes a plurality of elements and indicates an operation order on the plurality of quantum bits by an arrangement of each of the plurality of elements, and a second gate which indicates the predetermined operation; and generate a second quantum circuit by converting the first gate into a first equivalent circuit in the first quantum circuit and converting the second gate into a second equivalent circuit in which the plurality of elements are symmetrically moved in an arrangement direction of the plurality of first quantum bit.

What is claimed is: 
     
         1 . A quantum circuit design apparatus comprising:
 a memory; and   a processor coupled to the memory and configured to:   detect a first gate indicating a predetermined operation on a plurality of first quantum bits among a plurality of quantum bits included in a first quantum circuit, which includes a plurality of elements and indicates an operation order on the plurality of quantum bits by an arrangement of each of the plurality of elements, and a second gate which indicates the predetermined operation; and   generate a second quantum circuit by converting the first gate into a first equivalent circuit in the first quantum circuit and converting the second gate into a second equivalent circuit in which the plurality of elements are symmetrically moved in an arrangement direction of the plurality of first quantum bit.   
     
     
         2 . The quantum circuit design apparatus according to  claim 1 , wherein
 the predetermined operation is an operation which inverts a phase of one target bit of the plurality of first quantum bits in accordance with two control bits of the plurality of first quantum bits.   
     
     
         3 . The quantum circuit design apparatus according to  claim 2 , wherein
 the processor converts a third gate which inverts a bit of the one target bit of the plurality of first quantum bits in accordance with the two control bits of the plurality of first quantum bits into a third equivalent circuit including the predetermined operation.   
     
     
         4 . The quantum circuit design apparatus according to  claim 3 , wherein
 the processor converts a fourth gate which inverts a bit of one target bit of a plurality of second quantum bits including the plurality of first quantum bits in accordance with three or more control bits of the plurality of second quantum bits into a fourth equivalent circuit including the third gate.   
     
     
         5 . A non-transitory computer-readable recording medium storing a quantum circuit design program causing a computer to execute a processing of:
 detecting a first gate indicating a predetermined operation on a plurality of first quantum bits among a plurality of quantum bits included in a first quantum circuit, which includes a plurality of elements and indicates an operation order on the plurality of quantum bits by an arrangement of each of the plurality of elements, and a second gate which indicates the predetermined operation; and   generate a second quantum circuit by converting the first gate into a first equivalent circuit in the first quantum circuit and converting the second gate into a second equivalent circuit in which the plurality of elements are symmetrically moved in an arrangement direction of the plurality of first quantum bit.   
     
     
         6 . A quantum circuit design method comprising:
 detecting a first gate indicating a predetermined operation on a plurality of first quantum bits among a plurality of quantum bits included in a first quantum circuit, which includes a plurality of elements and indicates an operation order on the plurality of quantum bits by an arrangement of each of the plurality of elements, and a second gate which indicates the predetermined operation; and   generate a second quantum circuit by converting the first gate into a first equivalent circuit in the first quantum circuit and converting the second gate into a second equivalent circuit in which the plurality of elements are symmetrically moved in an arrangement direction of the plurality of first quantum bit.