Semiconductor structure

Abstract

A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height different than the first cell height, a plurality of third logic cells having the first cell height, and a plurality of metal lines parallel to each other in a metal layer. Each of the first logic cells includes a plurality of multiple-fin transistors. Each of the second logic cells includes a plurality of single-fin transistors. Each of the third logic cells includes a plurality of single-fin transistors. The first logic cells and the third logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a plurality of first logic cells having a first cell height, each comprising a plurality of multiple-fin transistors;   a plurality of second logic cells having a second cell height, each comprising a plurality of single-fin transistors, wherein the second cell height is different than the first cell height;   a plurality of third logic cells having the first cell height, each comprising a plurality of single-fin transistors; and   a plurality of metal lines parallel to each other in a metal layer,   wherein the first logic cells and the third logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array,   wherein the metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells.   
     
     
         2 . The semiconductor structure as claimed in  claim 1 , wherein the second cell height of the second logic cell is less than the first cell height of the first and third logic cells. 
     
     
         3 . The semiconductor structure as claimed in  claim 1 , wherein the metal lines covering the first and second logic cells are wider than the metal lines inside the first and second logic cells, and the metal lines covering the third and second logic cells are wider than the metal lines inside the second and third logic cells. 
     
     
         4 . The semiconductor structure as claimed in  claim 1 , wherein a plurality of first vias of a via layer under and coupled to the metal lines inside the first or third logic cells have larger size than a plurality of second vias of the via layer under and coupled to the metal lines inside the second logic cells. 
     
     
         5 . The semiconductor structure as claimed in  claim 1 , wherein width ratio of the metal lines covering the first and second logic cells to the metal lines inside the first logic cells is greater than 1.2, and width ratio of the metal lines inside the first logic cells to the metal lines inside the second logic cells is greater than 1.05. 
     
     
         6 . The semiconductor structure as claimed in  claim 1 , wherein a quantity of the metal lines inside the first or third logic cells is greater than that of the metal lines inside the second logic cells. 
     
     
         7 . A semiconductor structure, comprising:
 a plurality of first logic cells having a first cell height, each comprising a plurality of first fin transistors; and   a plurality of second logic cells having a second cell height, each comprising a plurality of second fin transistors, wherein the second cell height is different than the first cell height;   wherein the first logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array,   wherein a fin number of each of the first fin transistors in the first logic cells is greater than a fin number of each of the second fin transistors in the second logic cells.   
     
     
         8 . The semiconductor structure as claimed in  claim 7 , wherein the second cell height of the second logic cell is less than the first cell height of the first logic cells. 
     
     
         9 . The semiconductor structure as claimed in  claim 7 , further comprising:
 a plurality of metal lines parallel to each other in a metal layer,   wherein the metal lines covering the first and second logic cells are wider than the metal lines inside the first and second logic cells.   
     
     
         10 . The semiconductor structure as claimed in  claim 9 , wherein a plurality of first vias of a via layer under and coupled to the metal lines inside the first logic cells have larger size than a plurality of second vias of the via layer under and coupled to the metal lines inside the second logic cells. 
     
     
         11 . The semiconductor structure as claimed in  claim 9 , wherein a quantity of the metal lines inside the first logic cells is greater than that of the metal lines inside the second logic cells. 
     
     
         12 . A semiconductor structure, comprising:
 a plurality of first logic cells having a first cell height, each comprising a plurality of first fin transistors;   a plurality of second logic cells having a second cell height, each comprising a plurality of second fin transistors, wherein the second cell height is different than the first cell height;   a plurality of third logic cells having the first cell height, each comprising a plurality of third fin transistors; and   wherein the first logic cells and the third logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array,   wherein a fin number of each of the first fin transistors in the first logic cells is greater than a fin number of each of the second fin transistors in the second logic cells and the third fin transistors in the third logic cells.   
     
     
         13 . The semiconductor structure as claimed in  claim 12 , wherein the first fin transistors comprises a plurality of multiple-fin transistors, and the second fin transistors comprises a plurality of single-fin transistors, and the second cell height of the second logic cell is less than the first cell height of the first logic cell. 
     
     
         14 . The semiconductor structure as claimed in  claim 12 , wherein a plurality of first vias of a via layer under and coupled to the metal lines inside the first logic cells have larger size than a plurality of second vias of the via layer under and coupled to the metal lines inside the second logic cells. 
     
     
         15 . The semiconductor structure as claimed in  claim 12 , further comprising:
 a plurality of metal lines parallel to each other in a metal layer,   wherein a width ratio of the metal lines covering the first and second logic cells to the metal lines inside the first logic cells is greater than 1.2, and a width ratio of the metal lines inside the first logic cells to the metal lines inside the second logic cells is greater than 1.05.   
     
     
         16 . The semiconductor structure as claimed in  claim 12 , further comprising:
 a plurality of metal lines parallel to each other in a metal layer,   wherein a quantity of the metal lines inside the first logic cells is greater than that of the metal lines inside the second logic cells.   
     
     
         17 . The semiconductor structure as claimed in  claim 12 , wherein the first logic cells in the same row are isolated from each other by a dielectric material, and the second logic cells in the same row are isolated from each other by the dielectric material. 
     
     
         18 . The semiconductor structure as claimed in  claim 17 , wherein the dielectric material comprises a plurality of segments parallel to each other. 
     
     
         19 . The semiconductor structure as claimed in  claim 12 , wherein one of the first logic cells is adjacent to one of the third logic cells, and two adjacent second logic cells are located adjacent to the one of the first logic cells and the one of the third logic cells. 
     
     
         20 . The semiconductor structure as claimed in  claim 19 , wherein a sum of lengths of the one of the first logic cells and the one of the third logic cells is substantially equal to a sum of lengths of the two adjacent second logic cells.