Computing circuit, computing method, and decoder

Abstract

A computing circuit is provided. The computing circuit is disposed in a memory device and electrically coupled to a memory cell of the memory device. The computing circuit includes a weight decoder, a multiplier, an adder tree, and an accumulator. The weight decoder is configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight. The multiplier is configured to generate a partial-product by multiplying an input signal with the decoded weight. The adder tree is configured to generate a partial-sum by performing an addition operation based on the partial-product. The accumulator is configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum. The accumulated sum is left shifted based on a shift signal.

What is claimed is: 
     
         1 . A computing circuit, disposed in a memory device and electrically coupled to a memory cell of the memory device, wherein the computing circuit comprises:
 a weight decoder, configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight;   a multiplier, coupled to the weight decoder and configured to generate a partial-product by multiplying an input signal with the decoded weight;   an adder tree, coupled to the multiplier and configured to generate a partial-sum by performing an addition operation based on the partial-product; and   an accumulator, coupled to the adder tree and configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum,   wherein the accumulated sum is left shifted based on a shift signal.   
     
     
         2 . The memory test circuit according to  claim 1 , wherein
 the accumulator is configured to left shift the accumulated sum of a previous clock cycle based on the shift signal to generate a left-shifted accumulated sum of the previous clock cycle, and   the accumulator is configured to accumulate the left-shifted accumulated sum of the previous clock cycle with the partial-sum of a current clock cycle to generate the accumulated sum of the current clock cycle.   
     
     
         3 . The memory test circuit according to  claim 1 , wherein
 the weight decoder is configured to decode the compressed weight during a plurality of clock cycles to generate the decoded weight, wherein a number of the plurality clock cycles is same as a number of bits of the compressed weight.   
     
     
         4 . The memory test circuit according to  claim 1 , wherein
 the weight decoder is configured to obtain the decoded weight bitwise from a most significant bit (MSB) of the compressed weight to a least significant bit (LSB) of the compressed weight, respectively, at each clock cycle of a plurality of clock cycles, and   the weight decoder is configured to convert an undetermined bit of the decoded weight to a determined bit based on each bit of the compressed weight, respectively, at the each clock cycle of the plurality of clock cycles.   
     
     
         5 . The memory test circuit according to  claim 4 , wherein
 the weight decoder is configured to determine the undetermined bit of the decoded weight as zero after a last clock cycle of decoding.   
     
     
         6 . The memory test circuit according to  claim 4 , wherein
 the weight decoder is configured to determine the undetermined bit of the decoded weight to have a same value as the MSB after a last clock cycle of decoding.   
     
     
         7 . The memory test circuit according to  claim 1 , wherein
 the input signal is obtained wordwise at one clock cycle.   
     
     
         8 . The memory test circuit according to  claim 1 , wherein
 the compressed weight comprises a prefix, a run-length, and a postfix,   wherein the prefix indicates a MSB of an original weight, the run-length indicates a number of bits right after the MSB of the original weight having the same value as the MSB, and the postfix indicates the data of the original weight that is not represented by the prefix and the run-length.   
     
     
         9 . The memory test circuit according to  claim 8 , wherein
 the weight decoder is configured to store a multiplicand table, wherein the multiplicand table comprises a plurality of multiplicands corresponding to the prefix, the run-length, and the postfix of the compressed weight.   
     
     
         10 . The memory test circuit according to  claim 9 , wherein
 the weight decoder is configured to output a decoded multiplicand as the decoded weight corresponding to on the compressed weight based on multiplicand table.   
     
     
         11 . A computing method, adapted to a compute-in-memory (CIM) device, wherein the computing method comprises:
 obtaining a compressed weight from a memory cell of the CIM device;   generating a decoded weight based on the compressed weight;   generating a partial-product by multiplying an input signal with the decoded weight;   generating a partial-sum by performing an addition operation based on the partial-product;   generating an accumulated sum by performing an accumulation operation based on the partial-sum; and   outputting an output signal based on the accumulated sum,   wherein the accumulated sum is left shifted based on a shift signal.   
     
     
         12 . The computing method according to  claim 11 , further comprising:
 left-shifting the accumulated sum of a previous clock cycle based on the shift signal to generate a left-shifted accumulated sum of the previous clock cycle; and   accumulating the left-shifted accumulated sum of the previous clock cycle with the partial-sum of a current clock cycle to generate the accumulated sum of the current clock cycle.   
     
     
         13 . The computing method according to  claim 11 , further comprising:
 decoding the compressed weight during a plurality of clock cycles to generate the decoded weight, wherein a number of the plurality clock cycles is same as a number of bits of the compressed weight.   
     
     
         14 . The computing method according to  claim 11 , further comprising:
 obtaining the decoded weight bitwise from a most significant bit (MSB) of the compressed weight to a least significant bit (LSB) of the compressed weight, respectively, at each clock cycle of a plurality of clock cycles; and   converting an undetermined bit of the decoded weight to a determined bit based on each bit of the compressed weight, respectively, at the each clock cycle of the plurality of clock cycles.   
     
     
         15 . The computing method according to  claim 14 , further comprising:
 determining the undetermined bit of the decoded weight as zero after a last clock cycle of decoding.   
     
     
         16 . The computing method according to  claim 14 , further comprising:
 determining the undetermined bit of the decoded weight to have a same value as the MSB after a last clock cycle of decoding.   
     
     
         17 . The computing method according to  claim 11 , wherein
 the compressed weight comprises a prefix, a run-length, and a postfix,   wherein the prefix indicates a MSB of an original weight, the run-length indicates a number of bits right after the MSB of the original weight having the same value as the MSB, and the postfix indicates the data of the original weight that is not represented by the prefix and the run-length.   
     
     
         18 . A decoder for a compute-in-memory (CIM) device, wherein the decoder is configured to:
 decode a compressed weight, wherein the compressed weight comprises a prefix, a run-length, and a postfix, the prefix indicates a MSB of an original weight, the run-length indicates a number of bits right after the MSB of the original weight having the same value as the MSB, and the postfix indicates the data of the original weight that is not represented by the prefix and the run-length; and   generate a decoded weight based on the compress weight.   
     
     
         19 . The decoder according to  claim 18 , wherein the decoder is further configured to:
 store a multiplicand table, wherein the multiplicand table comprises a plurality of multiplicands corresponding to the prefix, the run-length, and the postfix of the compressed weight.   
     
     
         20 . The decoder according to  claim 19 , wherein the decoder is configured to:
 output a decoded multiplicand as the decoded weight corresponding to on the compressed weight based on multiplicand table.