Semiconductor memory devices and method of manufacturing the same

Abstract

A semiconductor memory device of the present invention is capable of high performance and high integration, and has an effect of configuring a semiconductor die including a vertical volatile memory structure and a vertical nonvolatile memory structure on one peripheral circuit structure. A semiconductor memory device provided includes a semiconductor substrate, a back gate structure having a cylindrical shape and extending in a vertical direction on the semiconductor substrate and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer, a plurality of semiconductor patterns, each having a ring-shaped horizontal section surrounding the back gate structure, and spaced apart from each other in the vertical direction, and first to third conductive lines surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a semiconductor substrate;   a back gate structure having a cylindrical shape and extending in a vertical direction on the semiconductor substrate and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer;   a plurality of semiconductor patterns, each having a ring-shaped horizontal section surrounding the back gate structure, and spaced apart from each other in the vertical direction;   first to third conductive lines surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction; and   a front gate insulating layer disposed to continuously surround between the semiconductor pattern and the second conductive line, on an upper surface of the second conductive line, and on a lower surface of the second conductive line,   wherein a region of the semiconductor patterns facing the first and third conductive lines is doped with a first-conductivity-type impurity,   wherein a region of the semiconductor patterns facing the second conductive line is doped with second-conductivity-type impurity of an opposite type to the first-conductivity-type impurity.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the semiconductor patterns are each composed of a source region, a channel region, and a drain region, arranged in sequence in the vertical direction,
 wherein the source region faces the first conductive line and is doped with an N-type impurity,   wherein the channel region faces the second conductive line and is doped with a P-type impurity,   wherein the drain region faces the third conductive line and is doped with an N-type impurity.   
     
     
         3 . The semiconductor memory device of  claim 2 , wherein a length of each of the source region, the channel region, and the drain region along the vertical direction is greater than a thickness of each of the corresponding first to third conductive lines. 
     
     
         4 . The semiconductor memory device of  claim 1 , further comprising a channel isolation insulating layer disposed between adjacent semiconductor patterns among the plurality of semiconductor patterns,
 wherein the channel isolation insulating layer comprises a horizontal part having a first thickness and an edge part having a second thickness greater than the first thickness,   wherein the plurality of semiconductor patterns are electrically separated from each other by the edge part of the channel isolation insulating layer.   
     
     
         5 . The semiconductor memory device of  claim 4 , wherein upper and lower surfaces of the edge part of the channel isolation insulating layer have a round shape. 
     
     
         6 . The semiconductor memory device of  claim 1 , further comprising a plurality of line insulating layers disposed between the first to third conductive lines, below the first conductive line, and above the third conductive line. 
     
     
         7 . The semiconductor memory device of  claim 6 , wherein a sidewall of each of the first and third conductive lines is in contact with the semiconductor pattern,
 wherein a sidewall of the second conductive line is in contact with the front gate insulating layer.   
     
     
         8 . The semiconductor memory device of  claim 1 , wherein a plurality of the second conductive lines are disposed to face one back gate structure,
 wherein the semiconductor memory device is configured such that holes are accumulated for a preset time in a region of the back gate insulating layer facing the second conductive lines.   
     
     
         9 . The semiconductor memory device of  claim 1 , wherein a line-shaped first interconnection line is disposed on the back gate structure,
 wherein a first via is disposed at a point where the back gate structure and the first interconnection line overlap.   
     
     
         10 . The semiconductor memory device of  claim 9 , wherein an upper surface of the first via is in contact with the first interconnection line,
 wherein a lower surface of the first via is in contact with the back gate electrode layer.   
     
     
         11 . A semiconductor memory device comprising:
 a semiconductor substrate having a cell region and a stepped extension region;   a back gate structure having a cylindrical shape and extending in a vertical direction on the semiconductor substrate, in the cell region, and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer;   a plurality of semiconductor patterns, each having a ring-shaped horizontal section surrounding the back gate structure, and spaced apart from each other in the vertical direction;   a source line, a word line, and a bit line, which surround the semiconductor pattern and spaced apart from each other in the vertical direction;   a front gate insulating layer disposed continuously between the semiconductor pattern and the word line, on an upper surface of the word line, and on a lower surface of the word line; and   a first interconnection line electrically connected to the back gate structure, on an upper portion of the cell region; and   a second interconnection line electrically connected to the source line, the word line, and the bit line, on an upper portion of the extension region,   wherein a region of the semiconductor patterns facing the source line and the bit line is doped with a first-conductivity-type impurity,   wherein a region of the semiconductor patterns facing the word line is doped with a second-conductivity-type impurity of an opposite type to the first-conductivity-type impurity.   
     
     
         12 . The semiconductor memory device of  claim 11 , wherein each of the semiconductor patterns comprises a source region, a channel region, and a drain region, sequentially arranged in the vertical direction,
 wherein the source region faces the source line, and a thickness of the source region in the vertical direction is greater than a thickness of the source line in the vertical direction,   wherein the channel region faces the word line, and a thickness of the channel region in the vertical direction is greater than a thickness of the word line in the vertical direction,   wherein the drain region faces the bit line, and a thickness of the drain region in the vertical direction is greater than a thickness of the bit line in the vertical direction.   
     
     
         13 . The semiconductor memory device of  claim 11 , further comprising a channel isolation insulating layer including: a horizontal part having a first thickness in the vertical direction; and an edge part having a second thickness in the vertical direction greater than the first thickness,
 wherein the plurality of semiconductor patterns are separated apart from each other in the vertical direction by the edge part of the channel isolation insulating layer.   
     
     
         14 . The semiconductor memory device of  claim 11 , wherein, in the cell region, a first via is disposed at a point where the back gate structure and the first interconnection line vertically overlap,
 wherein an upper surface of the first via is in contact with the first interconnection line,   wherein a lower surface of the first via is in contact with the back gate electrode layer.   
     
     
         15 . The semiconductor memory device of  claim 11 , wherein, in the extension region, a horizontal length of the source line is longer than a horizontal length of the word line and the horizontal length of the word line is longer than a horizontal length of the bit line, and
 wherein the source line, the word line, and the bit line face the same semiconductor pattern.   
     
     
         16 . The semiconductor memory device of  claim 15 , wherein, in the extension region, a plurality of second vias electrically connect respective the source line, the word line, and the bit line to the second interconnection line, the second via electrically connected to the source line is longer than the second via electrically connected to the word line, and the second via electrically connected to the word line is longer than the second via electrically connected to the bit line. 
     
     
         17 . The semiconductor memory device of  claim 11 , wherein the first interconnection line and the second interconnection line are not electrically connected to each other. 
     
     
         18 . A semiconductor memory device comprising:
 a semiconductor substrate;   a peripheral circuit structure disposed on the semiconductor substrate;   a volatile memory structure and a nonvolatile memory structure, disposed on the peripheral circuit structure,   wherein the volatile memory structure is a vertical dynamic random access memory (DRAM) and comprises:   a back gate structure having a cylindrical shape and extending in a vertical direction on the semiconductor substrate and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer;   a plurality of semiconductor patterns, each having a ring-shaped horizontal section surrounding the back gate structure, and spaced apart from each other in the vertical direction;   a source line, a word line, and a bit line, which horizontally surround the semiconductor pattern and spaced apart from each other in the vertical direction; and   a front gate insulating layer disposed continuously between the semiconductor pattern and the word line, on an upper surface of the word line, and on a lower surface of the word line,   wherein the nonvolatile memory structure is a vertical NAND.   
     
     
         19 . The semiconductor memory device of  claim 18 , further comprising a channel isolation insulating layer disposed between adjacent semiconductor patterns among the plurality of semiconductor patterns in the volatile memory structure,
 wherein the channel isolation insulating layer comprises: a horizontal part having a first thickness in the vertical direction; and an edge part having a second thickness in the vertical direction greater than the first thickness,   wherein the plurality of semiconductor patterns are electrically separated from each other by the edge part of the channel isolation insulating layer.   
     
     
         20 . The semiconductor memory device of  claim 18 , wherein the volatile memory structure is a capacitorless DRAM.