Semiconductor device

Abstract

A semiconductor device includes an active pattern extending in a first direction; a plurality of channel layers spaced apart from each other on the active pattern in a vertical direction and including lower channel layers and upper channel layers; an intermediate insulating layer between an uppermost lower channel layer and a lowermost upper channel layer; a gate structure intersecting the active pattern and the plurality of channel layers, and extending in a second direction intersecting the first direction; a lower source/drain region on a first side of the gate structure and connected to the lower channel layers; a blocking structure on a second side of the gate structure and connected to the lower channel layers; and an upper source/drain region on at least one side of the gate structure.

1 . A semiconductor device, comprising:
 an active pattern extending in a first direction on a substrate;   a plurality of channel layers spaced apart from each other on the active pattern in a direction perpendicular to an upper surface of the substrate and including lower channel layers and upper channel layers on the lower channel layers;   an intermediate insulating layer between an uppermost lower channel layer among the lower channel layers and a lowermost upper channel layer among the upper channel layers;   a gate structure intersecting the active pattern, extending in a second direction intersecting the first direction, and on the plurality of channel layers;   a lower source/drain region on a first side of the gate structure and connected to the lower channel layers;   a blocking structure on a second side of the gate structure and connected to the lower channel layers; and   an upper source/drain region on at least one of the first side or the second side of the gate structure and connected to the upper channel layers.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the blocking structure comprises:
 an insulating liner extending from a portion of the active pattern on the second side of the gate structure along side surfaces of the lower channel layers; and   an insulating gap-fill portion on the insulating liner.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the insulating liner has a lower region having a first thickness and an upper region having a second thickness that is smaller than the first thickness. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the insulating liner comprises silicon nitride, silicon oxynitride, or silicon carbonitride, and the insulating gap-fill portion comprises silicon oxide. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the blocking structure is on a portion of the active pattern on the second side of the gate structure and comprises an insulating gap-fill portion connected to side surfaces of the lower channel layers. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the insulating gap-fill portion comprises silicon nitride, silicon oxynitride, or silicon carbonitride. 
     
     
         7 . The semiconductor device of  claim 1 ,
 wherein the upper source/drain region is connected to the upper channel layers on the first side of the gate structure, and   wherein the blocking structure extends to the upper channel layers on the second side of the gate structure.   
     
     
         8 .- 11 . (canceled) 
     
     
         12 . The semiconductor device of  claim 1 ,
 wherein the semiconductor device further comprises a first interlayer insulating layer on the lower source/drain region and the blocking structure, and a second interlayer insulating layer between the first interlayer insulating layer and the upper source/drain region, and   wherein portions of each of the first and second interlayer insulating layer separate the upper source/drain region from the lower source/drain region and the blocking structure.   
     
     
         13 . The semiconductor device of  claim 1 , further comprising:
 a lower contact connected to the lower source/drain region, and an upper contact connected to the upper source/drain region.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the lower contact comprises a first horizontal contact portion connected to the lower source/drain region and extending in a horizontal direction parallel to the upper surface of the substrate, and a first vertical contact portion connected to the first horizontal contact portion and extending in the direction perpendicular to the upper surface of the substrate. 
     
     
         15 . The semiconductor device of  claim 14 , further comprising:
 a first buried electrode in the substrate,
 wherein the first vertical contact portion extends toward the substrate and is connected to the first buried electrode. 
   
     
     
         16 . The semiconductor device of  claim 13 , further comprising:
 a second buried electrode buried in the substrate,
 wherein the upper contact comprises a second horizontal contact portion connected to the upper source/drain region and extending in a horizontal direction parallel to the upper surface of the substrate, and a second vertical contact portion connecting the second horizontal contact portion to the second buried electrode. 
   
     
     
         17 . A semiconductor device, comprising:
 an active pattern extending in a first direction on a substrate;
 first lower channel layers on a first region of the active pattern and spaced apart from each other in a direction perpendicular to an upper surface of the substrate; 
 second lower channel layers on a second region of the active pattern and spaced apart from each other in the direction perpendicular to the upper surface of the substrate; 
 third lower channel layers on a third region of the active pattern and spaced apart from each other in the direction perpendicular to the upper surface of the substrate; 
 first, second, and third intermediate insulating layers on uppermost lower channel layers of the first, second, and third lower channel layers, respectively; 
 first, second, and third upper channel layers stacked and spaced apart from each other on the first, second, and third intermediate insulating layers, respectively; 
 a first gate structure intersecting the first region of the active pattern, extending in a second direction intersecting the first direction and on the first lower channel layers and the first upper channel layers; 
 a second gate structure intersecting the second region of the active pattern, extending in the second direction and on the second lower channel layers and the second upper channel layers; 
 a third gate structure intersecting the third region of the active pattern, extending in the second direction and on the third lower channel layers and the third upper channel layers; 
 a first lower source/drain region between the first and second gate structures and connected to the first and second lower channel layers; 
 a first upper source/drain region between the first and second gate structures and connected to the first and second upper channel layers; and 
 a blocking structure between the second and third gate structures, wherein the blocking structure is between the second and third lower channel layers and/or is between the second and third upper channel layers. 
   
     
     
         18 . The semiconductor device of  claim 17 ,
 wherein the blocking structure comprises a lower blocking structure between the second and third lower channel layers, and   wherein the semiconductor device further comprises a second upper source/drain region connected to the second and third upper channel layers between the second and third gate structures.   
     
     
         19 . The semiconductor device of  claim 18 , further comprising:
 a first interlayer insulating layer on the first lower source/drain region and the blocking structure, and a second interlayer insulating layer on the first interlayer insulating layer and on the first and second upper source/drain regions, and   wherein portions of the first and second interlayer insulating layers separate the first and second upper source/drain regions from the first lower source/drain region and the blocking structure, respectively.   
     
     
         20 . The semiconductor device of  claim 17 ,
 wherein the blocking structure comprises an upper blocking structure between the second and third upper channel layers, and   wherein the semiconductor device further comprises a second lower source/drain region connected to the second and third lower channel layers between the second and third gate structures.   
     
     
         21 . The semiconductor device of  claim 17 , wherein the blocking structure extends from between the second and third lower channel layers to between the second and third upper channel layers. 
     
     
         22 . A semiconductor device, comprising:
 a first transistor structure on a substrate; and   a second transistor structure on the first transistor structure,   wherein the first transistor structure comprises:
 first channel layers stacked and spaced apart from each other on the substrate in a vertical direction perpendicular to an upper surface of the substrate; 
 a first gate electrode on the first channel layers; 
 a first source/drain region on a first side of the first gate electrode and connected to first side surfaces of the first channel layers; and 
 a blocking structure on the first channel layers on a second side of the first gate electrode, 
   wherein the second transistor structure comprises:
 second channel layers on the first channel layers and stacked and spaced apart from each other in the vertical direction; 
 a second gate electrode on the second channel layers; 
 first and second upper source/drain regions on first and second sides of the second gate electrode and connected to opposing side surfaces of the second channel layers, respectively. 
   
     
     
         23 . The semiconductor device of  claim 22 ,
 wherein the blocking structure comprises an insulating liner extending from an upper surface portion of the substrate on the second side of the first gate electrode along side surfaces of the first channel layers, and an insulating gap-fill portion on the insulating liner, and   wherein the insulating liner comprises silicon nitride, silicon oxynitride, or silicon carbonitride, and the insulating gap-fill portion comprises silicon oxide.   
     
     
         24 . (canceled) 
     
     
         25 . The semiconductor device of  claim 22 , wherein the blocking structure comprises:
 an insulating gap-fill portion on an upper surface portion of the substrate on the second side of the first gate electrode and connected to second side surfaces of the first channel layers,   wherein the insulating gap-fill portion comprises silicon nitride, silicon oxynitride, or silicon carbonitride.