Techniques for a memory module per row activate counter

Abstract

Examples include techniques for a memory module per row activate counter. The techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. The activate count is maintained by a controller for the memory module. Detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.

What is claimed is: 
     
         1 . An apparatus on a memory module comprising:
 a command and address (CA) interface to couple with a CA bus that is coupled to a memory controller; and   circuitry to:
 receive, via the CA interface, an activate (ACT) command sent over the CA bus from the memory controller, the ACT command to indicate a row address to activate at a volatile memory device on the memory module; 
 increment an activate count for the row address to generate an updated activate count; 
 compare the updated activate count to a threshold count; and 
 cause an alert message to be sent to the memory controller if the updated activate count matches the threshold count. 
   
     
     
         2 . The apparatus of  claim 1 , further comprising the circuitry to:
 block the command from being forwarded to the volatile memory device if the updated activate count matches the threshold count.   
     
     
         3 . The apparatus of  claim 1 , further comprising the circuitry to:
 reset the activate count for the row address if the updated activate count matches the threshold count.   
     
     
         4 . The apparatus of  claim 1 , wherein the memory module comprises a dual in-line memory module (DIMM) and the volatile memory device is a dynamic random access memory (DRAM) device. 
     
     
         5 . The apparatus of  claim 1 , wherein the apparatus is a registering clock driver (RCD) resident on the DIMM. 
     
     
         6 . The apparatus of  claim 1 , wherein the alert message sent to the memory controller causes the memory controller to issue a directed refresh management (DRFM) command to the volatile memory device, the DRFM command to cause the volatile memory device to refresh row addresses at the volatile memory device that are adjacent to the row address indicated in the ACT command. 
     
     
         7 . The apparatus of  claim 1 , wherein to cause the alert message to be sent to the memory controller if the updated activate count matches the threshold count further comprises the circuitry to issue a directed refresh management (DRFM) command to the volatile memory device, the DRFM command to cause the volatile memory device to refresh row addresses at the volatile memory device that are adjacent to the row address indicated in the ACT command. 
     
     
         8 . The apparatus of  claim 7 , wherein the alert message sent to the memory controller indicates that the DRFM command has been issued to the volatile memory device. 
     
     
         9 . A method comprising:
 receiving, at controller circuitry on a memory module, an activate (ACT) command sent over a command and address bus from a memory controller, the ACT command to indicate a row address to activate at a volatile memory device on the memory module;   incrementing an activate count for the row address to generate an updated activate count;   comparing the updated activate count to a threshold count; and   causing an alert message to be sent to the memory controller if the updated activate count matches the threshold count.   
     
     
         10 . The method of  claim 9 , wherein the memory module comprises a dual in-line memory module (DIMM) and the volatile memory device is a dynamic random access memory (DRAM) device. 
     
     
         11 . The method of  claim 10 , wherein the controller circuitry is included in a registering clock driver (RCD) resident on the DIMM. 
     
     
         12 . The method of  claim 9 , wherein the alert message sent to the memory controller causes the memory controller to send a directed refresh management (DRFM) command to the volatile memory device, the DRFM command to cause the volatile memory device to refresh row addresses at the volatile memory device that are adjacent to the row address indicated in the ACT command. 
     
     
         13 . The method of  claim 9 , wherein causing the alert message to be sent to the memory controller if the updated activate count matches the threshold count further comprises issuing a directed refresh management (DRFM) command to the volatile memory device, the DRFM command to cause the volatile memory device to refresh row addresses at the volatile memory device that are adjacent to the row address indicated in the ACT command. 
     
     
         14 . A memory module comprising:
 a plurality of volatile memory devices; and   a controller that includes a command and address (CA) interface to couple with a CA bus that is coupled to a memory controller and includes circuitry, wherein the circuitry is configured to:
 receive, via the CA interface, an activate (ACT) command sent over the CA bus from the memory controller, the ACT command to indicate a row address to activate at a volatile memory device from among the plurality of volatile memory devices; 
 increment an activate count for the row address to generate an updated activate count; 
 compare the updated activate count to a threshold count; and 
 cause an alert message to be sent to the memory controller if the updated activate count matches the threshold count. 
   
     
     
         15 . The memory module of  claim 14 , further comprising the circuitry to:
 block the command from being forwarded to the volatile memory device if the updated activate count matches the threshold count.   
     
     
         16 . The memory module of  claim 14 , wherein the memory module comprises a dual in-line memory module (DIMM) and the plurality of volatile memory devices are dynamic random access memory (DRAM) devices. 
     
     
         17 . The memory module of  claim 16 , wherein the controller is a registering clock driver (RCD). 
     
     
         18 . The memory module of  claim 14 , wherein the alert message sent to the memory controller causes the memory controller to issue a directed refresh management (DRFM) command to the volatile memory device, the DRFM command to cause the volatile memory device to refresh row addresses at the volatile memory devices that are adjacent to the row address indicated in the ACT command. 
     
     
         19 . The memory module of  claim 14 , wherein to cause the alert message to be sent to the memory controller if the updated activate count matches the threshold count further comprises the circuitry to issue a directed refresh management (DRFM) command to the volatile memory device, the DRFM command to cause the volatile memory device to refresh row addresses at the volatile memory devices that are adjacent to the row address indicated in the ACT command. 
     
     
         20 . The memory module of  claim 19 , wherein the alert message sent to the memory controller indicates that the DRFM command has been issued to the volatile memory device.