Semiconductor device including mosfet region and diode region and manufacturing method thereof

Abstract

Disclosed are a semiconductor device (1) including a MOSPET region and an integrated diode region, and a manufacturing method thereof. More particularly, a semiconductor device (1) including a silicon carbide (SiC) MOSPET region and an integrated Schottky bather diode that reduce forward voltage drop (Vf), device area, and switching oscillation resulting from parasitic inductance are disclosed.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate including a MOSFET region and a Schottky bather diode (SBD) region;   a lightly doped second conductivity type drift region on the substrate in the MOSFET region and the SBD region;   a first conductivity type well in the drift region in the MOSFET region;   a heavily doped second conductivity type source in the well;   a gate in the MOSFET region and comprising a gate insulating film on the drift region and a gate electrode on the gate insulating film; and   a JFET region in the drift region and below the gate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the MET region surrounds or is in contact with one sidewall and a lowermost surface of the well. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a first high concentration impurity region in contact with the source and the well in the MOSFET region and the JFET region, the first high concentration impurity region having a first conductive type; and   a first ohmic contact at least partially in contact with the source and the first high concentration impurity region.   
     
     
         4 . The semiconductor device of  claim 3 , further comprising a second high concentration impurity region in the drift region in the SBD region, the second high concentration impurity region having the first conductivity type. 
     
     
         5 . The semiconductor device of  claim 4 , further comprising a second ohmic contact on the second high concentration impurity region in the SBD region. 
     
     
         6 . The semiconductor device of  claim 4 , further comprising a contact region on the drift region in the SBD region. 
     
     
         7 . A semiconductor device, comprising:
 a substrate having a plurality of MOSPET regions and one or more Schottky bather diode (SBD) regions;   a lightly doped second conductivity type drift region on the substrate in the MOSPET regions and the one or more SBD regions; and   a plurality of unit cells having a first substantially hexagonal shape and at least a partial honeycomb structure, the unit cells comprising the MOSPET regions;   wherein the one or more SBD regions are between at least two of the unit cells and have a second substantially hexagonal shape.   
     
     
         8 . The semiconductor device of  claim 7 , wherein each of the unit cells comprises:
 a gate having a third substantially hexagonal shape;   a well in the drift region and below the gate;   a source in contact with the well in the drift region;   a first high concentration impurity region surrounded by the source in the drift region, the first high concentration impurity region having a first conductivity type; and   a JFET region in the drift region and below the gate.   
     
     
         9 . The semiconductor device of  claim 7 , comprising a plurality of the SBD regions, wherein the SBD regions are not in contact with each other. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the one or more SBD regions has six outer surfaces in contact with respective unit cells. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the one or more SBD regions comprises:
 a second high concentration impurity region in the drift region, the second high concentration impurity region having the first conductivity type; and   a second ohmic contact on the second high concentration impurity region.   
     
     
         12 . The semiconductor device of  claim 11 , further comprising:
 a source metal or source electrode covering the gate on the drift region; and   a drain metal or drain electrode under the substrate.   
     
     
         13 . A semiconductor device, comprising:
 a substrate having a plurality of MOSPET regions and one or more Schottky bather diode (SBD) regions;   a lightly doped second conductivity type drift region on the substrate in the MOSPET regions and the one or more SBD regions; and   a plurality of unit cells having a first substantially hexagonal shape and at least a partial honeycomb structure, and arranged in n columns, the unit cells comprising the MOSPET regions;   wherein the one or more SBD regions are between two or more of the unit cells, have a second substantially hexagonal shape, and are not in adjacent ones of the n columns.   
     
     
         14 . The semiconductor device of  claim 13 , wherein each of the one or more SBD regions is directly surrounded by a subset of the plurality of the unit cells. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the one or more SBD regions alternate with the unit cells in at least one of the n columns. 
     
     
         16 . The semiconductor device of  claim 15 , wherein the SBD regions have an area equal to or less than 25% or less of a total area of an active region. 
     
     
         17 . The semiconductor device of  claim 13 , further comprising a heavily doped first conductivity type impurity region in the drift region and in a center of each of the one or more SBD regions. 
     
     
         18 . A method of manufacturing a semiconductor device, comprising:
 forming a drift region on a substrate;   forming unit cells in n columns, the unit cells comprising MOSPET regions; and   forming SBD regions,   wherein forming the unit cells comprises:
 forming second conductivity type JFET regions having a substantially hexagonal shape in the drift region and in the MOSPET regions; 
 forming first conductivity type wells in the JFET regions; 
 forming first high concentration impurity regions in the JFET regions in contact with the wells, the first high concentration impurity regions having a first conductivity type; 
 forming first heavily doped second conductivity type sources in the wells; 
 forming second heavily doped second conductivity type sources in the drift region; and 
 forming gates having a substantially hexagonal shape on the JFET regions, the wells, and the sources to having at least a partial honeycomb structure. 
   
     
     
         19 . The method of  claim 18 , wherein the SBD regions are not in contact with each other. 
     
     
         20 . The method of  claim 18 , wherein the SBD regions are not in consecutive ones of the n columns.