Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a lower substrate including a lower interconnection layer;   an upper substrate on the lower substrate, including
 a first surface and a second surface opposite to each other; 
 a recessed surface having a step difference from the second surface; 
 a through-hole extending from the recessed surface to the first surface and 
 an upper interconnection layer electrically connected to the lower interconnection layer; 
   a semiconductor chip disposed between the recessed surface of the upper substrate and the lower substrate, and including connection pads electrically connected to the lower interconnection layer;   an interconnect structure disposed between the second surface of the upper substrate and the lower substrate, and electrically connecting the lower interconnection layer to the upper interconnection layer; and   an insulating member including a first portion covering at least a portion of each of the semiconductor chip and the interconnect structure between the upper substrate and the lower substrate, a second portion extending from the first portion into the through-hole, and a third portion extending from the second portion and covering at least a portion of the first surface of the upper substrate.   
     
     
         2 . The semiconductor package of  claim 1 , wherein
 bump structures electrically connected to the connection pads of the semiconductor chip,   wherein the first portion configured to encapsulate at least a portion of the bump structures.   
     
     
         3 . The semiconductor package of  claim 2 , wherein the bump structures are spaced apart from each other with an equal distance therebetween. 
     
     
         4 . The semiconductor package of  claim 1 , wherein a width of a lower end of the third portion in contact with the first surface of the upper substrate is greater than a diameter of the through-hole. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the through-hole extends perpendicular to the recessed surface. 
     
     
         6 . The semiconductor package of  claim 1 , wherein a width of the recessed surface is greater than a width of the semiconductor chip. 
     
     
         7 . The semiconductor package of  claim 1 , further comprising:
 an upper package disposed on the upper substrate; and   upper connection bumps electrically connecting the upper package to the upper interconnection layer,   wherein a height of the third portion is lower than a height of the upper connection bumps.   
     
     
         8 . A semiconductor package, comprising:
 a lower substrate including a lower interconnection layer;   a semiconductor chip disposed on the lower substrate and electrically connected to the lower interconnection layer;   an upper substrate disposed on the semiconductor chip and including interconnection pads surrounding a region overlapping the semiconductor chip, and at least one through-hole spaced apart from the interconnection pads;   at least one mold line disposed on the upper substrate and spaced apart from the interconnection pads and extending in a first direction from the through-hole;   an encapsulant configured to encapsulate at least a portion of the semiconductor chip between the upper substrate and the lower substrate and connected to the mold line through the through-hole.   
     
     
         9 . The semiconductor package of  claim 8 , wherein the at least one through-hole includes a plurality of through-holes spaced apart from each other in the first direction. 
     
     
         10 . The semiconductor package of  claim 9 , wherein the plurality of through-holes are aligned in a row in the first direction. 
     
     
         11 . The semiconductor package of  claim 10 , wherein at least some of through-holes among the plurality of through-holes partially overlap in the first direction. 
     
     
         12 . The semiconductor package of  claim 8 , wherein the at least one through-hole includes a plurality of through-holes spaced apart from each other in a second direction intersecting the first direction. 
     
     
         13 . The semiconductor package of  claim 12 , wherein the at least one mold line includes a plurality of mold lines spaced apart from each other and extending in the first direction from the plurality of through-holes. 
     
     
         14 . The semiconductor package of  claim 13 , wherein at least some of the interconnection pads are disposed between an adjacent pair of the plurality of mold lines. 
     
     
         15 . The semiconductor package of  claim 8 , wherein the at least one mold line extends to at least one side end of the upper substrate in a first direction. 
     
     
         16 . A method of manufacturing a semiconductor package, the method comprising:
 disposing a semiconductor chip on a preliminary lower substrate;   preparing a preliminary upper substrate having a recessed surface and a through-hole extending from the recessed surface, wherein the recessed surface has a step difference from a lower surface of the preliminary upper substrate;   forming interconnect structures between the preliminary lower substrate and the preliminary upper substrate;   introducing a flux cleaning liquid between the preliminary lower substrate and the preliminary upper substrate and through the through-hole; and   forming an encapsulating layer encapsulating at least a portion of each of the semiconductor chip and the interconnect structures and a preliminary mold line connected to the encapsulating layer through the through-hole by filling an insulating material between the preliminary lower substrate and the preliminary upper substrate that extends through the through-hole.   
     
     
         17 . The method of  claim 16 , further comprising:
 disposing a mold frame on the preliminary upper substrate after spraying the flux cleaning liquid,   wherein the mold frame has an inner groove extending in the first direction.   
     
     
         18 . The method of  claim 16 ,
 wherein the insulating material is transferred in the first direction, and   wherein the preliminary mold line extends in the first direction.   
     
     
         19 . The method of  claim 18 , wherein the void formed in the process of filling the insulating material is discharged to the preliminary upper substrate through the through-hole. 
     
     
         20 . The method of  claim 16 , further comprising:
 cutting each of the preliminary lower substrate, the encapsulating layer, the preliminary mold line, and the preliminary upper substrate into one unit after the forming the preliminary mold line.