Gate cut, with asymmetrical channel to gate cut spacing

Abstract

An integrated circuit includes a first device and a laterally adjacent second device. The first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. The second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. A gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. In an example, the first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a first semiconductor device comprising (i) a first source region, (ii) a first drain region, (iii) a first body comprising semiconductor material extending in a first direction from the first source region to the first drain region, and (iv) a first gate structure extending in a second direction and on the first body;   a second semiconductor device comprising (i) a second source region, (ii) a second drain region, (iii) a second body comprising semiconductor material extending in the first direction from the second source region to the second drain region, and (iv) a second gate structure extending in the second direction and on the second body; and   a gate cut laterally between and separating the first gate structure and the second gate structure, the gate cut comprising dielectric material;   wherein the first body is separated laterally from the gate cut by a first distance, wherein the second body is separated laterally from the gate cut by a second distance, and wherein the first and second distances differ by at least 2 nanometers (nm).   
     
     
         2 . The integrated circuit of  claim 1 , wherein there is no other semiconductor device between the first semiconductor device and the gate cut, and between the second semiconductor device and the gate cut. 
     
     
         3 . The integrated circuit of  claim 1 , wherein:
 the first gate structure comprises (i) a gate electrode, and (ii) a gate dielectric on the first body, the gate dielectric separating the gate electrode from the first body; and   the gate dielectric, and not the gate electrode, is laterally between the first body and the dielectric material of the gate cut.   
     
     
         4 . The integrated circuit of  claim 1 , wherein the first distance is zero, such that the first body is in contact with the dielectric material of the gate cut. 
     
     
         5 . The integrated circuit of  claim 1 , wherein:
 the first gate structure comprises (i) a gate electrode, and (ii) gate dielectric between the gate electrode and the first body; and   the gate dielectric is in contact with the dielectric material of the gate cut.   
     
     
         6 . The integrated circuit of  claim 1 , wherein:
 the first gate structure comprises (i) a gate electrode, and (ii) gate dielectric between the gate electrode and the first body; and   no portion of the gate electrode is laterally between at least a section of the first body and the dielectric material of the gate cut.   
     
     
         7 . The integrated circuit of  claim 1 , wherein the gate cut is a first gate cut, and wherein the integrated circuit further comprises:
 a third semiconductor device comprising (i) a third source region, (ii) a third drain region, (iii) a third body comprising semiconductor material extending in the first direction from the third source region to the third drain region, and (iv) a third gate structure extending in the second direction and on the third body, wherein the second semiconductor device is laterally between the first and third semiconductor devices; and   a second gate cut laterally between and separating the second gate structure and the third gate structure, the second gate cut comprising the dielectric material, wherein there is no other semiconductor device between the second semiconductor device and the second gate cut;   wherein the second body is separated laterally from the second gate cut by a third distance, and wherein the second and third distances differ by at least 2 nm.   
     
     
         8 . The integrated circuit of  claim 7 , wherein the first gate cut has a first width measured in the second direction, the second gate cut has a second width measured in the second direction, and the first and second widths differ by at least 2 nm. 
     
     
         9 . The integrated circuit of  claim 1 , wherein at least one of the first or second distances is less than 2 nm. 
     
     
         10 . The integrated circuit of  claim 1 , wherein the first and second distances differ by at least 4 nm. 
     
     
         11 . The integrated circuit of  claim 1 , wherein each of the first and second bodies is a nanoribbon, a nanowire, or a nanosheet. 
     
     
         12 . The integrated circuit of  claim 1 , wherein each of the first and second bodies is a fin. 
     
     
         13 . The integrated circuit of  claim 1 , wherein the first device comprises:
 a plurality of bodies arranged in a vertical stack and comprising semiconductor material, the plurality of bodies extending in the first direction from the first source region to the first drain region, the plurality of bodies including the first body,   wherein the first gate structure at least in part wraps around middle portions of each body of the plurality of bodies, and   wherein the plurality of bodies comprises a plurality of nanoribbons, a plurality of nanowires, or a plurality of nanosheets.   
     
     
         14 . A printed circuit board comprising the integrated circuit of  claim 1 . 
     
     
         15 . An integrated circuit comprising:
 a semiconductor device comprising (i) a source region, (ii) a drain region, (iii) a body comprising semiconductor material extending laterally from the source region to the drain region, and (iv) a gate structure on the body; and   a first gate cut and a second gate cut, each of the first and second gate cuts comprising dielectric material, wherein the gate structure is laterally between and in contact with the first and second gate cuts;   wherein no other semiconductor device is laterally between the semiconductor device and the first gate cut, and laterally between the semiconductor device and the second gate cut;   wherein the body is separated laterally from (i) the first gate cut by a first distance and (ii) the second gate cut by a second distance; and   wherein the first and second distances differ by at least 2 nanometers (nm).   
     
     
         16 . The integrated circuit of  claim 15 , wherein the gate structure comprises (i) a gate electrode, and (ii) gate dielectric between the gate electrode and the body, and wherein the gate dielectric is in contact with the dielectric material of one of the first or second gate cuts. 
     
     
         17 . The integrated circuit of  claim 15 , wherein the gate structure comprises (i) a gate electrode, and (ii) gate dielectric between the gate electrode and the body, and wherein the gate electrode in part wraps around a middle section of the body, and the gate electrode is absent laterally between at least a section of the body and the dielectric material of one of the first or second gate cuts. 
     
     
         18 . An integrated circuit comprising:
 a first device including a first body comprising semiconductor material, and a second device including a second body comprising semiconductor material, wherein the first and second devices include a first gate structure that is on both the first body and the second body;   a third device including (i) a third body comprising semiconductor material, and (ii) a second gate structure on the third body;   a fourth device including (i) a fourth body comprising semiconductor material, and (ii) a third gate structure on the fourth body, wherein the first gate structure is laterally between the second and third gate structures;   a first structure comprising dielectric material laterally between the first and second gate structures, wherein there is no intervening device laterally between the first device and the first structure; and   a second structure comprising dielectric material laterally between the first and third gate structures, wherein there is no intervening device laterally between the second device and the second structure;   wherein the first body is separated laterally from the first structure by a first distance and the second body is separated laterally from the second structure by a second distance; and   wherein the first and second distances differ by at least 2 nanometers (nm).   
     
     
         19 . The integrated circuit of  claim 18 , further comprising:
 a fifth device laterally between the first device and the second device, wherein the fifth device includes a fifth body comprising semiconductor material, and wherein the first gate structure is on the fifth body.   
     
     
         20 . The integrated circuit of  claim 18 , wherein:
 the third body is separated laterally from the first structure by a third distance, and the fourth body is separated laterally from the second structure by a fourth distance; and   the first and third distances differ by at least 2 nm, and/or the second and fourth distances differ by at least 2 nm.