FinFET Device and Method of Forming Same

Abstract

A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, removing a portion of the fin adjacent the dummy gate structure to form a first recess, depositing a stressor material in the first recess, removing at least a portion of the stressor material from the first recess, and after removing the at least a portion of the stressor material, epitaxially growing a source/drain region in the first recess.

What is claimed is: 
     
         1 . A method comprising:
 forming a first recess in a substrate;   depositing one or more material layers in the first recess;   after depositing the one or more material layers, annealing the substrate   after annealing, removing a first portion of the one or more material layers using a first etching process, wherein a second portion of the one or more material layers remains on a bottom of the first recess after the first etching process;   after removing the first portion of the one or more material layers, removing at least a portion of the second portion of the one or more material layers using a second etching process, wherein the second etching process exposes a bottom of the first recess; and   after removing the second portion of the one or more material layers, forming a semiconductor material in the first recess.   
     
     
         2 . The method of  claim 1 , wherein the annealing imparts a tensile stress in the substrate. 
     
     
         3 . The method of  claim 1 , wherein the annealing imparts a compressive stress in the substrate. 
     
     
         4 . The method of  claim 1 , wherein forming the one or more material layers comprises:
 depositing a first dielectric layer in the first recess; and   depositing a second dielectric layer over the first dielectric layer in the first recess.   
     
     
         5 . The method of  claim 4 , further comprising:
 after depositing the first dielectric layer and prior to depositing the second dielectric layer, annealing the first dielectric layer.   
     
     
         6 . The method of  claim 4 , wherein depositing the first dielectric layer comprises depositing a first material using a first set of process parameters, wherein depositing the second dielectric layer comprises depositing the first material using a second set of process parameters, wherein the first set of process parameters is different than the second set of process parameters. 
     
     
         7 . The method of  claim 6 , wherein the first material comprises silicon nitride. 
     
     
         8 . The method of  claim 1 , further comprising:
 after removing the first portion of the one or more material layers, and prior to removing at least the portion of the second portion of the one or more material layers using the second etching process, forming an etch stop layer and an interlayer dielectric layer over the etch stop layer.   
     
     
         9 . A method comprising:
 forming a first recess in a semiconductor structure;   forming a stressor material in the first recess;   forming a dielectric layer over the stressor material;   forming an opening in the dielectric layer, the opening exposing exposed portions of the stressor material;   annealing the semiconductor structure while the stressor material is in the first recess;   after forming the opening and after annealing, removing the exposed portions of the stressor material to expose the semiconductor structure; and   after removing the exposed portions of the stressor material, forming a semiconductor material in the first recess.   
     
     
         10 . The method of  claim 9 , further comprising forming a gate structure over the semiconductor structure, wherein the first recess in the semiconductor structure is adjacent the gate structure. 
     
     
         11 . The method of  claim 10 , wherein the gate structure is a dummy gate structure. 
     
     
         12 . The method of  claim 9 , wherein the stressor material comprises silicon nitride. 
     
     
         13 . The method of  claim 9 , wherein the semiconductor material forms a source/drain region. 
     
     
         14 . The method of  claim 9 , wherein annealing the semiconductor structure is performed prior to forming the dielectric layer. 
     
     
         15 . The method of  claim 9 , wherein forming the stressor material comprises forming a plurality of stressor layers. 
     
     
         16 . A method comprising:
 performing a first etching process on a substrate to form a first recess;   forming a first dielectric material within the first recess;   performing a first anneal process on the first dielectric material, the first dielectric material providing a stress to sidewalls of the first recess after the first anneal process;   removing a first portion of the first dielectric material;   forming a second dielectric material over remaining portions of the first dielectric material;   forming an opening through the second dielectric material to expose the remaining portions of the first dielectric material;   removing at least a portion of the remaining portions of the first dielectric material; and   forming a semiconductor material in the first recess.   
     
     
         17 . The method of  claim 16 , further comprising, prior to removing the first portion of the first dielectric material:
 forming a third dielectric material within the first recess on the first dielectric material; and   performing a second anneal process on the third dielectric material.   
     
     
         18 . The method of  claim 16 , further comprising forming a buffer layer within the first recess, wherein the first dielectric material is formed over the buffer layer. 
     
     
         19 . The method of  claim 16 , wherein forming the semiconductor material is performed while the second dielectric material remains. 
     
     
         20 . The method of  claim 16 , wherein removing the portion of the remaining portions of the first dielectric material removes all remaining portions of the first dielectric material in the first recess.