Integrated circuit package and method

Abstract

A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 forming a first bonding layer over a substrate of a first wafer, the first wafer comprising a first semiconductor die and a second semiconductor die;   performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die;   performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, wherein the trench is disposed between the two grooves; and   thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.   
     
     
         2 . The method of  claim 1 , further comprising:
 bonding the first semiconductor die and the second semiconductor die to a second wafer, wherein the first wafer comprises first bonding pads in the first bonding layer, wherein the second wafer comprises second bonding pads in a second bonding layer, and wherein the bonding comprises:
 bonding the first bonding pads to the second bonding pads using direct metal-to-metal bonding; and 
 bonding the first bonding layer to the second bonding layer using direct oxide-to-oxide bonding. 
   
     
     
         3 . The method of  claim 1 , wherein the two grooves also extend partially through the substrate of the first wafer. 
     
     
         4 . The method of  claim 3 , wherein the two grooves have a first depth measured from a point that is level with a top surface of the first bonding layer to a bottom surface of the two grooves, and the trench has a second depth measured from a point that is level with a top surface of the first bonding layer to a bottom surface of the trench, and wherein the second depth is greater than the first depth. 
     
     
         5 . The method of  claim 4 , wherein the first depth is in a range from 10 μm to 50 μm. 
     
     
         6 . The method of  claim 1 , wherein the first dicing process comprises a plasma dicing process, and the second dicing process comprises a blade dicing process. 
     
     
         7 . The method of  claim 6 , wherein the first dicing process comprises deep reactive ion etching (DRIE) using a fluorine plasma. 
     
     
         8 . A method of manufacturing a semiconductor device, the method comprising:
 forming a first bonding layer over a substrate of a first wafer, the first wafer comprising a plurality of top dies; and   singulating the first wafer to separate each of the plurality of top dies from other top dies of the plurality of top dies, wherein singulating the first wafer comprises:
 performing a plasma dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between adjacent top dies of the plurality of top dies; 
 performing a blade dicing process to form a trench along a dicing path that extends through the first bonding layer and partially through the substrate of the first wafer, wherein the dicing path extends into portions of the two grooves; and 
 grinding a backside of the substrate of the first wafer to remove a material of the substrate of the first wafer that is below the trench. 
   
     
     
         9 . The method of  claim 8 , wherein during the plasma dicing process the first bonding layer and top portions of the first wafer are removed in corner regions of each of the plurality of top dies. 
     
     
         10 . The method of  claim 9 , wherein each of the corner regions is adjacent to a first sidewall of a corresponding top die of the plurality of top dies, wherein each first sidewall of the corresponding top die is adjacent to a second sidewall of the corresponding top die, wherein each first sidewall of the corresponding top die is also adjacent to a third sidewall of the corresponding top die, and wherein the first sidewall of the corresponding top die is slanted in a top down view such that it is not be disposed at a right angle relative to the second sidewall of the corresponding top die and the third sidewall of the corresponding top die. 
     
     
         11 . The method of  claim 10 , wherein a first angle between the first sidewall of the corresponding top die and the second sidewall of the corresponding top die is in a range from 130° to 140°, and a second angle between the first sidewall of the corresponding top die and the second sidewall of the corresponding top die is in a range from 130° to 140°. 
     
     
         12 . The method of  claim 8 , wherein the plasma dicing process comprises an etching process that uses fluorine plasma as an etchant. 
     
     
         13 . The method of  claim 8 , wherein a width of each of the first groove and the second groove is in a range from 10 μm to 50 μm. 
     
     
         14 . The method of  claim 8 , wherein performing the plasma dicing process comprises:
 forming a first groove of the two grooves adjacent to a first sidewall of a first top die of the plurality of top dies; and   forming a second groove adjacent to a second sidewall of the first top die, wherein the first sidewall of the first top die is on an opposite side of the first top die as the second sidewall of the first top die.   
     
     
         15 . A package comprising:
 a first die over and bonded to a wafer, wherein a first dielectric layer of the first die is directly bonded to a second dielectric layer of the wafer, wherein the first die comprises;
 a bottom portion of the first die; and 
 a top portion of the first die, wherein the top portion extends laterally beyond sidewalls of the bottom portion of the first die by a width that is up to 5 μm, wherein a corner region of the bottom portion of the first die comprises:
 a first sidewall; 
 a second sidewall connected to the first sidewall; and 
 a third sidewall connected to the first sidewall, a first angle between the first sidewall and the second sidewall is greater than 90°; 
 
   through substrate vias (TSVs) extending through a portion of the wafer; and   a redistribution structure on a backside of the wafer, wherein the redistribution structure is electrically connected to the first die through the TSVs.   
     
     
         16 . The package of  claim 15  further comprising a package substrate coupled to the redistribution structure using conductive connectors. 
     
     
         17 . The package of  claim 15 , wherein a height of the bottom portion of the first die is in a range from 10 μm to 50 μm. 
     
     
         18 . The package of  claim 15  further comprising:
 a molding compound surrounding the bottom portion of the first die and the top portion of the first die, wherein the molding compound is disposed between the second dielectric layer and a bottom surface of the top portion of the first die. 
 
     
     
         19 . The package of  claim 15 , wherein a material of the top portion of the first die is different from materials of the bottom portion of the first die. 
     
     
         20 . The package of  claim 15 , wherein the first angle between the first sidewall of the bottom portion of the first die and the second sidewall of the bottom portion of the first die is in a range from 130° to 140°, and wherein a second angle between the first sidewall of the bottom portion of the first die and the third sidewall of the bottom portion of the first die is in a range from 130° to 140°.