US2024096702A1PendingUtilityA1

Semiconductor apparatus and manufacturing method of semiconductor apparatus

Assignee: TOSHIBA KKPriority: Sep 20, 2022Filed: Sep 19, 2023Published: Mar 21, 2024
Est. expirySep 20, 2042(~16.1 yrs left)· nominal 20-yr term from priority
H10W 90/734H10W 20/20H10W 20/023H10W 72/30H01L 21/76898H01L 23/481H01L 24/32H01L 2224/32225
53
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A manufacturing method of a semiconductor apparatus according to an embodiment includes forming an electrode on a first main surface of a semiconductor substrate made from a compound semiconductor; forming, at a location where the electrode is formed, a via hole that penetrates the first main surface and a second main surface of the semiconductor substrate, wherein a ratio of a thickness of the semiconductor substrate to a maximum value of a width of an opening in the second main surface is greater than 1; forming a rear-side electrode on a second main surface of the semiconductor substrate in such a manner that the rear-side electrode is electrically coupled to the electrode in the via hole; forming an insulating layer arranged at least a layer above the opening; and forming a solder layer in a layer above the rear-side electrode and the insulating layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A manufacturing method of a semiconductor apparatus, comprising:
 forming an electrode on a first main surface of a semiconductor substrate made from a compound semiconductor;   forming, at a location where the electrode is formed, a via hole that penetrates the first main surface and a second main surface of the semiconductor substrate, wherein a ratio of a thickness of the semiconductor substrate to a maximum value of a width of an opening in the second main surface is greater than 1;   forming a rear-side electrode on a second main surface of the semiconductor substrate in such a manner that the rear-side electrode is electrically coupled to the electrode in the via hole;   forming an insulating layer arranged at least a layer above the opening; and   forming a solder layer in a layer above the rear-side electrode and the insulating layer.   
     
     
         2 . The manufacturing method of a semiconductor apparatus according to  claim 1 , wherein
 the forming the insulating layer includes:   forming an insulating film on the rear-side electrode and performing anisotropic etching on the insulating film in a thickness direction of the semiconductor substrate.   
     
     
         3 . The manufacturing method of a semiconductor apparatus according to  claim 1 , wherein
 the forming the insulating layer includes:   forming an insulating film on the rear-side electrode and polishing the insulating film arranged on a layer above the second main surface of the semiconductor substrate.   
     
     
         4 . The manufacturing method of a semiconductor apparatus according to  claim 1 , wherein
 the forming the insulating layer includes:   forming an insulating film on the rear-side electrode, forming a resist pattern that covers a part of the insulating film formed in the via hole and in the vicinity of the opening, removing the insulating film exposed from the resist pattern by etching, and removing the resist pattern.   
     
     
         5 . A semiconductor apparatus further comprising:
 a semiconductor substrate having a via hole penetrating a first main surface and a second main surface;   an electrode arranged above a via hole on the first main surface of the semiconductor substrate;   a rear-side electrode arranged on the second main surface of the semiconductor substrate and electrically coupled to the electrode in the via hole; and   an insulating layer arranged on the rear-side electrode in at least part of the via hole, wherein   a ratio of a thickness of the semiconductor substrate to a maximum value of a width of an opening of the via hole is greater than 1.   
     
     
         6 . The semiconductor apparatus according to  claim 5 , further comprising:
 a solder layer arranged on the rear-side electrode and the insulating layer; and   a void surrounded at least by the solder layer and the insulating layer in the via hole.

Join the waitlist — get patent alerts

Track US2024096702A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.