Three-dimensional flash memory including floating devices, and manufacturing method therefor

Abstract

A three-dimensional flash memory including floating devices and a manufacturing method therefor are disclosed. A method for manufacturing a three-dimensional flash memory according to an embodiment may comprise the steps of: preparing a semiconductor structure including a plurality of word lines and a plurality of interlayer insulating layers, which are alternately stacked in a vertical direction while extending in a horizontal direction, respectively, and at least one memory cell string formed extending through the plurality of word lines and the plurality of interlayer insulating layers in the vertical direction, wherein the at least one memory cell string constitutes a plurality of memory cells corresponding to the plurality of word lines, while including a channel layer formed extending in the vertical direction, a charge storage layer formed to surround the channel layer, and a floating device layer formed extending to surround the charge storage layer; removing the plurality of interlayer insulating layers from the semiconductor structure; and removing regions of the floating device layer corresponding to the plurality of interlayer insulating layers, in order to form a plurality of floating devices isolated from each other.

What is claimed is: 
     
         1 . A method of manufacturing a three-dimensional (3D) flash memory including a floating device, the method comprising:
 preparing a semiconductor structure including a plurality of word lines and a plurality of interlayer insulating layers that are alternately stacked in a vertical direction while each extending in a horizontal direction, at least one memory cell string that is formed extending by passing through the plurality of word lines and the plurality of interlayer insulating layers in the vertical direction, the at least one memory cell string constituting a plurality of memory cells corresponding to the plurality of word lines while including a channel layer formed extending in the vertical direction, a charge storage layer formed to surround the channel layer, and a floating device layer formed extending to surround the charge storage layer;   removing the plurality of interlayer insulating layers from the semiconductor structure; and   removing regions corresponding to the plurality of interlayer insulating layers in the floating device layer to form a plurality of floating devices isolated from each other.   
     
     
         2 . The method of  claim 1 , wherein the removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer comprises removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer through a plurality of air gaps that are spaces in which the plurality of interlayer insulating layers are removed. 
     
     
         3 . The method of  claim 1 , wherein the removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer comprises removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer using a thermal oxidation process. 
     
     
         4 . The method of  claim 1 , wherein the removing the plurality of interlayer insulating layers and the removing the regions corresponding to the plurality of interlayer insulating layers in the floating device layer is performed through a single process. 
     
     
         5 . The method of  claim 1 , further comprising:
 forming a floating gate oxide layer in spaces in which regions corresponding to the plurality of interlayer insulating layers in the floating device layer are removed to isolate the plurality of memory cells from each other.