US2024087862A1PendingUtilityA1

Ion-to-electron conversion dynode for ion imaging applications

Assignee: THERMO FINNIGAN LLCPriority: Jul 29, 2019Filed: Nov 16, 2023Published: Mar 14, 2024
Est. expiryJul 29, 2039(~13 yrs left)· nominal 20-yr term from priority
H01J 43/246H01J 49/025H01J 49/0095
76
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A metal-channel conversion dynode comprises: a wafer comprising a first face and a second face parallel to the first face and having a thickness less than 1000 μm; and a plurality of channels passing through the wafer from the first face to the second face at an angle to a plane of the first face and a plane of the second face. In some embodiments, each inter-channel distance may be substantially the same as the wafer thickness. In some embodiments, the wafer is fabricated from tungsten. In some other embodiments, the wafer comprises a non-electrically conductive material that is fabricated by three-dimensional (3D) printing or other means and that is coated, on its faces and within its channels, with a metal or suitably conductive coating that produces secondary electrons upon impact by either positive or negative ions.

Claims

exact text as granted — not AI-modified
We claim: 
     
         1 . A method of fabricating a metal-channel conversion dynode that converts ions to secondary particles, the method comprising:
 fabricating a wafer having a thickness that is less than 1000 μm, the wafer comprising:
 a first face and a second face parallel to the first face; and 
 a plurality of channels passing through the wafer from the first face to the second face slanted at an angle to a plane of the first face and a plane of the second face; 
   wherein fabricating the wafer includes at least one of laser ablation micro-machining, wire electrical discharge machining (wire-EDM), three-dimensional (3D) printing, or stacking individual plates that include through-holes arranged in offset patterns.   
     
     
         2 . The method of  claim 1 , further comprising coating the wafer, on its faces and within its channels, with a metal coating. 
     
     
         3 . The method of  claim 1 , wherein the wafer comprises a non-electrically-conducting material. 
     
     
         4 . The method of  claim 1 , wherein fabricating the wafer includes fabricating a wafer comprising tungsten, molybdenum, or a tungsten or molybdenum alloy having chemical purity of 90-99%. 
     
     
         5 . The method of  claim 1 , wherein fabricating the wafer includes forming a plurality of slanted walls that define the plurality of channels. 
     
     
         6 . The method of  claim 5 , wherein forming the plurality of slanted walls includes forming a top surface of a first slanted wall in the plurality of slanted walls in alignment with a projection, normal to the first face and the second face of the wafer, of a bottom surface of a second slanted wall in the plurality of slanted walls. 
     
     
         7 . The method of  claim 1 , wherein forming the wafer includes placing an inter-channel distance between each channel in the plurality of channels that is substantially the same as the thickness of the wafer. 
     
     
         8 . The method of  claim 1 , wherein fabricating the wafer includes forming a square cross section for each channel of the plurality of channels at its intersection with each face. 
     
     
         9 . The method of  claim 1 , wherein fabricating the wafer using three-dimensional printing includes direct 3D printing using a 3D printer. 
     
     
         10 . The method of  claim 9 , wherein using the 3D printer includes fabricating the wafer, including the channels passing therethrough, by 3D printing of metal. 
     
     
         11 . The method of  claim 9 , wherein using the 3D printer includes fabricating the wafer, including the channels passing therethrough, by 3D printing of a non-conductive material. 
     
     
         12 . The method of  claim 1 , wherein the angle of the plurality of channels is in a range from 45 degrees to 60 degrees. 
     
     
         13 . The method of  claim 1 , wherein fabricating the wafer includes arranging the plurality of channels in a square-grid array. 
     
     
         14 . The method of  claim 13 , wherein the square-grid array is a 64 by 64 square-grid array. 
     
     
         15 . The method of  claim 1 , wherein the thickness of the wafer is in a range of 150-200 μm. 
     
     
         16 . The method of  claim 1 , wherein fabricating the wafer includes selecting the thickness and an inter-channel distance between channels in the plurality of channels to configure the conversion dynode to convert negative ions to secondary electrons that pass through the dynode while essentially all protons are neutralized within the plurality of channels.

Join the waitlist — get patent alerts

Track US2024087862A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.