Integrated circuit devices including a back side power distribution network structure and methods of forming the same

Abstract

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower insulating structure, a transistor on the lower insulating structure, the transistor including a source/drain region, a power rail structure in the lower insulating structure, and a power contact structure that is on the power rail structure and electrically connects the source/drain region to the power rail structure. The power contact structure may include a lower portion that is in the power rail structure.

What is claimed is: 
     
         1 . An integrated circuit device comprising:
 a lower insulating structure;   a transistor on the lower insulating structure, the transistor comprising a source/drain region;   a power rail structure in the lower insulating structure; and   a power contact structure that is on the power rail structure and electrically connects the source/drain region to the power rail structure,   wherein the power contact structure comprises a lower portion that is in the power rail structure.   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the power contact structure comprises a contact conductor and a contact barrier layer on an outer surface of the contact conductor, and
 the lower portion of the power contact structure is devoid of the contact barrier layer.   
     
     
         3 . The integrated circuit device of  claim 2 , wherein the contact barrier layer comprises a metal nitride layer. 
     
     
         4 . The integrated circuit device of  claim 2 , wherein a portion of the contact conductor in the power rail structure contacts the power rail structure. 
     
     
         5 . The integrated circuit device of  claim 1 , wherein the lower portion of the power contact structure has a convex surface. 
     
     
         6 . The integrated circuit device of  claim 1 , further comprising a first active region and a second active region in the lower insulating structure,
 wherein the source/drain region is on the first active region,   a portion of the lower insulating structure separates the first active region from the second active region, and   the power contact structure extends through the portion of the lower insulating structure.   
     
     
         7 . The integrated circuit device of  claim 6 , wherein the first and second active regions are spaced apart from each other in a first direction, and
 the power rail structure extends in a second direction that is perpendicular to the first direction.   
     
     
         8 . The integrated circuit device of  claim 6 , wherein the source/drain region comprises a lower surface facing the first active region and an upper surface opposite the lower surface, and
 the integrated circuit device further comprises a source/drain contact that contacts the upper surface of the source/drain region and the power contact structure.   
     
     
         9 . The integrated circuit device of  claim 1 , wherein the source/drain region comprises a lower surface facing the lower insulating structure and an upper surface opposite the lower surface, and
 the power contact structure contacts the lower surface of the source/drain region.   
     
     
         10 . The integrated circuit device of  claim 1 , further comprising a back-end-of-line (BEOL) structure including a conductive wire on the transistor,
 wherein the transistor is between the BEOL structure and the power rail structure.   
     
     
         11 . An integrated circuit device comprising:
 a power rail structure; and   a transistor and a power contact structure on the power rail structure,   wherein the transistor comprises a source/drain region,   the power contact structure electrically connects the power rail structure to the source/drain region, and   an interface between the power contact structure and the power rail structure is curved toward the power rail structure.   
     
     
         12 . The integrated circuit device of  claim 11 , wherein the power contact structure comprises a contact conductor and a contact barrier layer on an outer surface of the contact conductor, and
 the interface between the power contact structure and the power rail structure is devoid of the contact barrier layer.   
     
     
         13 . The integrated circuit device of  claim 12 , wherein the contact barrier layer comprises a metal nitride layer. 
     
     
         14 . The integrated circuit device of  claim 11 , further comprising a back-end-of-line (BEOL) structure including a conductive wire on the transistor,
 wherein the transistor is between the BEOL structure and the power rail structure.   
     
     
         15 . A method of forming an integrated circuit device, the method comprising:
 forming a transistor comprising a source/drain region on an upper surface of a substrate structure;   forming a power contact structure electrically connected to the source/drain region;   removing a lower portion of the substrate structure, wherein a lower portion of the power contact structure protrudes from a lower surface of the substrate structure after removing the lower portion of the substrate structure; and then   forming a power rail structure on the lower surface of the substrate structure, wherein the lower portion of the power contact structure is in the power rail structure.   
     
     
         16 . The method of  claim 15 , wherein the lower portion of the power contact structure has a convex surface. 
     
     
         17 . The method of  claim 15 , wherein the power contact structure comprises a contact conductor and a contact barrier layer that extends on a side and a lower surface of the contact conductor, and
 the method further comprises exposing a lower portion of the contact conductor by removing a lower portion of the contact barrier layer before forming the power rail structure, and the lower portion of the contact conductor contacts the power rail structure.   
     
     
         18 . The method of  claim 17 , further comprising rounding a surface of the lower portion of the contact conductor after exposing the lower portion of the contact conductor and before forming the power rail structure. 
     
     
         19 . The method of  claim 18 , wherein forming the power rail structure comprises:
 forming a deposition inhibition layer on the rounded surface of the lower portion of the contact conductor;   forming a rail barrier layer on the lower surface of the substrate structure, wherein the rail barrier layer is not formed on the deposition inhibition layer;   removing the deposition inhibition layer, thereby exposing the rounded surface of the lower portion of the contact conductor; and then   forming a rail conductor on the rail barrier layer, wherein the rail conductor contacts the rounded surface of the lower portion of the contact conductor.   
     
     
         20 . The method of  claim 18 , further comprising, before removing the lower portion of the substrate structure, forming a back-end-of-line (BEOL) structure including a conductive wire on the transistor.