Semiconductor device and method for fabricating the same

Abstract

Various embodiments of the present invention are to provide a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device including isolation layers including an air gap, thereby minimizing stress to a substrate caused by oxide and improving performance of a device, and a method for fabricating the same. The semiconductor device according to the embodiment of the present invention comprises: a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench; an active region including a fin body disposed between the isolation layers, which are consecutively disposed, and a fin formed on the fin body, the fin having a narrower width than the fin body and extending in a first direction; a gate structure partially covering the active region and the isolation layers, and extending in a second direction; and a source/drain region covering the fin on both sides of the gate structure.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor device, the method comprising:
 forming a plurality of stacked structures spaced apart from each other over a substrate and sequentially stacking fins and sacrificial patterns;   forming sacrificial spacers on both sides of each of the stacked structures;   etching an exposed portion of the substrate between adjacent sacrificial spacers to form a plurality of dividing trenches extending in a first direction and spaced apart in a second direction perpendicular to the first direction, the dividing trench defining an active region including a fin body having a width greater than a width of the fins and the fins on the fin body; and   forming an isolation layer in each of the plurality of the dividing trench, the isolation layer including an air gap and a capping layer.   
     
     
         2 . The method according to  claim 1 , wherein the forming a plurality of stacked structures includes:
 sequentially forming a fin material layer and first to third sacrificial layers over the substrate;   forming a mask pattern over the third sacrifice layer; and   sequentially etching the third sacrifice layer to the first sacrifice layer and the fin material layer using the mask pattern.   
     
     
         3 . The method according to  claim 1 , wherein the fin includes a semiconductor material. 
     
     
         4 . The method according to  claim 1 , wherein the sacrificial pattern includes an insulating material. 
     
     
         5 . The method according to  claim 1 , wherein the capping layer includes silicon oxide having a bad step coverage. 
     
     
         6 . The method according to  claim 1 , wherein the capping layer is one selected from USG oxide, TEOS oxide, and HDP oxide. 
     
     
         7 . The method according to  claim 1 , wherein each of the sacrificial spacers includes a material having an etch selectivity with respect to the substrate. 
     
     
         8 . The method according to  claim 1 , wherein each of the sacrificial spacers includes nitride or oxide. 
     
     
         9 . The method according to  claim 1 , wherein each of the sacrificial spacers includes any one of insulating materials selected from SiO2, SiON, SiBN, and SiBCN. 
     
     
         10 . The method according to  claim 1 , wherein each of the isolation layers has a width narrower than that of the fin body. 
     
     
         11 . The method according to  claim 1 , wherein an upper surface of the fin body and an upper surface of each of the isolation layers are at a same level. 
     
     
         12 . The method according to  claim 1 , wherein an upper surface of the fin is at a level higher than upper surfaces of the isolation layers. 
     
     
         13 . The method according to  claim 1 , wherein the fin body and the fin are made of different materials. 
     
     
         14 . The method according to  claim 1 , wherein a stacked structure of the fin/the fin body is one of stacked structures of semiconductor materials among SiGe/Si, Ge/Si, high concentration SiGe/low concentration SiGe, GeSn/Ge, and Sn/Ge. 
     
     
         15 . The method according to  claim 1 , further comprising:
 forming a gate structure partially covering the active region and the isolation layers, and extending in the second direction; and   forming a source/drain region covering the fin on both sides of the gate structure.   
     
     
         16 . The method according to  claim 1 , wherein the source/drain region includes the fin on both sides of the gate structure and an epitaxial layer grown from the fin. 
     
     
         17 . A method for fabricating a semiconductor device, the method comprising:
 forming a stacked structure of a fin and a sacrificial pattern on a substrate;   forming sacrificial spacers on both sides of the stacked structure;   forming a dividing trench by etching an exposed portion of the substrate between the sacrificial spacers, which are consecutively disposed; and   forming an isolation layer in the dividing trench, the isolation layer including an air gap and a capping layer.