Semiconductor die stacks and associated systems and methods

Abstract

Semiconductor devices and semiconductor device assemblies, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a support substrate, a first die package carried by the support substrate, and a second die package carried by the first die package. Each of the first and second die packages can include a first die, a second die hybrid bonded a surface of the first die, and a third die hybrid bonded to a surface of the second die. The first die is coupled to the third die via an interconnect portion of the second die. Further, the third die can include an array of active cells for each of the packages, the second die can include complementary-metal-oxide-semiconductor (CMOS) circuitry accessing the active cells, and the first die can include backend of line (BEOL) circuitry associated with the active cells and CMOS circuitry.

We claim: 
     
         1 . A semiconductor die package, comprising:
 a first semiconductor die comprising:
 a first semiconductor substrate having an inner surface and an outer surface opposite the inner surface; and 
 a plurality of metallization layers formed in the first semiconductor substrate; 
   a second semiconductor die comprising:
 a second semiconductor substrate having a front surface and a back surface opposite the front surface, wherein the back surface is hybrid bonded to the inner surface of the first semiconductor substrate; 
 complementary metal-oxide-semiconductor (CMOS) circuitry formed in the second semiconductor substrate at the front surface; and 
 an interconnect section electrically coupling the back surface to the front surface; and 
   a third semiconductor die comprising a third semiconductor substrate having an array of active cells formed therein, wherein:
 the third semiconductor substrate includes a front side and a back side opposite the front side, and 
 the front side includes conductive components, and wherein the front side is hybrid bonded to the front surface of the second semiconductor substrate to (1) provide the CMOS circuitry with access to the active cells and (2) electrically couple the active cells to the plurality of metallization layers through the interconnect section. 
   
     
     
         2 . The semiconductor die package of  claim 1  wherein the plurality of metallization layers form at least one signal route line between a first component in the CMOS circuitry and a second component in the active cells. 
     
     
         3 . The semiconductor die package of  claim 1  wherein the first semiconductor substrate has a first thickness, the second semiconductor substrate has a second thickness different than the first thickness, and the third semiconductor substrate has a third thickness different than the first thickness and the second thickness. 
     
     
         4 . The semiconductor die package of  claim 1  wherein the first semiconductor die includes a porch extending beyond a longitudinal footprint of the second semiconductor die and the third semiconductor die such that a portion of the inner surface of the first semiconductor substrate is exposed, and wherein the exposed portion includes one or more bond pads. 
     
     
         5 . The semiconductor die package of  claim 4  wherein the second semiconductor substrate and the third semiconductor substrate have a combined thickness that is greater than a height to which bond wires attached to the one or more bond pads rise above the inner surface of the first semiconductor substrate. 
     
     
         6 . The semiconductor die package of  claim 4 , further comprising:
 a support substrate, to which the outer surface of the first semiconductor substrate is attached, the support substrate including one or more substrate bond pads; and   one or more bond wires each coupling one of the one or more bond pads on the first semiconductor substrate with a corresponding one of the substrate bond pads.   
     
     
         7 . The semiconductor die package of  claim 1  wherein each of the first semiconductor die, the second semiconductor die, and the third semiconductor die have a generally equal longitudinal footprint. 
     
     
         8 . The semiconductor die package of  claim 1  wherein outer surface of the first semiconductor substrate includes one or more first bond pads, wherein the back side of the third semiconductor substrate includes one or more second bond pads individually aligned with a corresponding one of the one or more first bond pads, and wherein the third semiconductor die further comprises at least one interconnect electrically coupling the front side of the third semiconductor substrate to the back side. 
     
     
         9 . The semiconductor die package of  claim 1  wherein the plurality of metallization layers include conductive components at the outer surface of the first semiconductor substrate, and wherein the semiconductor die package further comprises:
 a fourth semiconductor die comprising:
 a fourth semiconductor substrate having a front surface and a back surface opposite the front surface of the fourth semiconductor substrate, wherein the back surface is hybrid bonded to the outer surface of the first semiconductor substrate; 
 additional CMOS circuitry formed in the fourth semiconductor substrate at the front surface of the fourth semiconductor substrate; and 
 an interconnect section electrically coupling the back surface of the fourth semiconductor to the front surface of the fourth semiconductor die; and 
 
 a fifth semiconductor die comprising a fifth semiconductor substrate having an array of additional active cells formed therein, wherein:
 the fifth semiconductor substrate includes a front side and a back side opposite the front side of the fifth semiconductor substrate, and 
 the front side of the fifth semiconductor substrate is hybrid bonded to the front surface of the fourth semiconductor substrate to (1) provide the additional CMOS circuitry with access to the additional active cells and (2) electrically couple the active cells to the plurality of metallization layers through the interconnect section of the fourth die. 
 
 
     
     
         10 . A semiconductor die assembly, comprising:
 a support substrate;   a first die package carried by the support substrate, the first die package comprising a first die having an inner surface and an outer surface, a second die having a back surface hybrid bonded to the inner surface of the first die and a front surface opposite the back surface, and a third die having a front side hybrid bonded to the front surface of the second die and a back side opposite the front side, wherein the first die is coupled to the third die via an interconnect portion of the second die, and wherein the first die package is electrically coupled to at least one first substrate bond pad on the support substrate; and   a second die package carried by the first die package, the second die package comprising a fourth die having an inner surface and an outer surface, a fifth die having a back surface hybrid bonded to the inner surface of the fourth die and a front surface opposite the back surface, and a sixth die having a front side hybrid bonded to the front surface of the fifth die and a back side opposite the front side, wherein the sixth die is coupled to the fourth die via an interconnect portion of the fifth die, and wherein the second die package is electrically coupled to at least one second substrate bond pad on the support substrate.   
     
     
         11 . The semiconductor die assembly of  claim 10  wherein the first die has a first thickness, the second die has a second thickness different than the first thickness, and the third die has a third thickness different than the first thickness and the second thickness. 
     
     
         12 . The semiconductor die assembly of  claim 10  wherein:
 the first die has an exposed portion extending beyond a footprint of the second die and the third die wherein the exposed portion of the first die includes a first bond pad; 
 the fourth die has an exposed portion that extends beyond a footprint of the fifth die and the sixth die, wherein the exposed portion of the fourth die includes a second bond pad; and 
 the semiconductor die assembly further comprises:
 a first bond wire electrically coupling the first bond pad to the at least one first substrate bond pad; and 
 a second bond wire electrically coupling the second bond pad to the at least one second substrate bond pad. 
 
 
     
     
         13 . The semiconductor die assembly of  claim 12  wherein the second die and the third die have a combined thickness that is greater than a height to which the first bond wire rises off the first bond pad. 
     
     
         14 . The semiconductor die assembly of  claim 10  wherein:
 the first die package further comprises a plurality of first bond pads on the outer surface of the first die and a plurality of second bond pads on the back surface of the third die, wherein each of the plurality of first bond pads is vertically aligned with a corresponding one of the plurality of second bond pads; and 
 the second die package further comprises a plurality of third bond pads on the outer surface of the fourth die and a plurality of fourth bond pads on the back surface of the sixth die, wherein each of the plurality of third bond pads is vertically aligned with a corresponding one of the plurality of fourth bond pads and a corresponding one of the plurality of second bond pads. 
 
     
     
         15 . The semiconductor die assembly of  claim 14  wherein each of the plurality of first bond pads is electrically coupled to a corresponding substrate bond pad on the support substrate via a solder structure, and wherein each of the plurality of third bond pads is electrically coupled to the corresponding one of the plurality of second bond pads via a solder structure. 
     
     
         16 . The semiconductor die assembly of  claim 10  wherein:
 the front surface of the second die and the front side of the third die each includes a plurality of conductive components, wherein individual ones of the plurality of conductive components of the second die are conjoined with corresponding individual ones of the plurality of conductive components of the third die; and 
 peripheral circuitry of the second die is configured to access an array of active cells of the third die through one or more conjoined conductive components of the plurality. 
 
     
     
         17 . A method of forming a semiconductor assembly, comprising:
 providing a first die having an inner surface and an outer surface, the first die comprising a plurality of metallization layers in a first semiconductor substrate;   providing a second die having a front surface and a back surface, the second die comprising complementary metal-oxide-semiconductor (CMOS) circuitry formed in a second semiconductor substrate at the front surface and an interconnect portion extending between the front surface and the back surface;   providing a third semiconductor die having a front side and a back side, the third die comprising an array of active cells formed in a second semiconductor substrate at the front side; and   conjoining the first die, the second die, and the third die together to form a semiconductor package, wherein:
 the inner surface of the first die is hybrid bonded to the back surface of the second die, wherein at least one first component of the first die is coupled to the interconnect portion, and 
 and the front surface of the second die is hybrid bonded to the front side of the third die to provide the CMOS circuitry with access to the active cells, wherein at least one second component of the third die is electrically coupled to the interconnect portion. 
   
     
     
         18 . The method of  claim 17  wherein the plurality of metallization layers in the first die form at least one signal route line between the CMOS circuitry in the second die and the active cells in the third die. 
     
     
         19 . The method of  claim 17 , further comprising attaching the semiconductor package to a support substrate having a plurality of substrate bond pads, wherein attaching the semiconductor package includes electrically coupling the third die to at least one of the plurality of substrate bond pads. 
     
     
         20 . The method of  claim 19 , further comprising stacking a second semiconductor package to the semiconductor package, wherein attaching the second semiconductor package includes electrically coupling the second semiconductor package to at least one of the plurality of substrate bond pads.