Manufacturing method of layout structure of storage cell

Abstract

A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.

What is claimed is: 
     
         1 . A method of forming a storage cell, comprising:
 forming a transistor on a semiconductor substrate;   forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor;   forming a bit line to couple the plurality of fuses; and   forming a word line to couple a control terminal of the transistor.   
     
     
         2 . The method of  claim 1 , wherein the plurality of fuses are connected in series between the bit line and the connecting terminal of the transistor. 
     
     
         3 . The method of  claim 1 , wherein forming the plurality of fuses in the at least one conductive layer on the semiconductor substrate to couple the first connecting terminal of the transistor comprises:
 forming a first fuse having a first conductive pad coupled to the connecting terminal of the transistor; and   forming a second fuse having a first conductive pad coupled to a second conductive pad of the first fuse, wherein a second conductive pad of the second fuse is coupled to the bit line.   
     
     
         4 . The method of  claim 3 , wherein the first fuse is disposed in a first conductive layer on the semiconductor substrate, the second fuse is disposed in a second conductive layer on the semiconductor substrate, and the second conductive layer is different from the first conductive layer. 
     
     
         5 . The method of  claim 3 , wherein the first fuse and the second fuse are disposed in a same conductive layer on the semiconductor substrate. 
     
     
         6 . The method of  claim 1 , wherein forming the plurality of fuses in the at least one conductive layer on the semiconductor substrate to couple the connecting terminal of the transistor comprises:
 forming a first fuse and a second fuse in a first conductive layer on the semiconductor substrate; and   forming a third fuse in a second conductive layer on the semiconductor substrate, wherein the second conductive layer is different from the first conductive layer.   
     
     
         7 . The method of  claim 6 , wherein the first fuse, the second fuse, and the third fuse are connected in series between the bit line and the connecting terminal of the transistor. 
     
     
         8 . A method of forming a storage cell, comprising:
 forming a transistor on a semiconductor substrate;   forming a first fuse in a first conductive layer over the semiconductor substrate;   forming a second fuse in a second conductive layer over the first conductive layer;   forming a bit line to couple to the first fuse and the second fuse; and   forming a word line to couple to a gate of the transistor.   
     
     
         9 . The method of  claim 8 , wherein the first fuse and the second fuse are connected in series between the bit line and a drain of the transistor. 
     
     
         10 . The method of  claim 9 , wherein the forming of the first fuse further comprises forming a first conductive pad of the first fuse to couple to the second fuse, and forming a second conductive pad of the first fuse to couple to the drain of the transistor. 
     
     
         11 . The method of  claim 10 , wherein the forming of the second fuse further comprises forming a third conductive pad of the second fuse to couple to the bit line, and forming a fourth conductive pad of the second fuse to couple to the first conductive pad of the first fuse. 
     
     
         12 . The method of  claim 11 , further comprising forming a metal line in a third conductive layer, wherein the third conductive layer is between the first conductive layer and the second conductive layer. 
     
     
         13 . The method of  claim 12 , wherein the fourth conductive pad of the second fuse is coupled to the first conductive pad of the first fuse through the metal line. 
     
     
         14 . The method of  claim 8 , further comprising forming a third fuse in the first conductive layer or in the second conductive layer. 
     
     
         15 . The method of  claim 14 , wherein the first fuse, the second fuse, and the third fuse are connected in series between the bit line and the transistor. 
     
     
         16 . A method of forming a storage cell, comprising:
 forming a transistor on a semiconductor substrate;   forming a first fuse and a second fuse in a first conductive layer over the semiconductor substrate;   forming a bit line to couple to the first fuse and the second fuse; and   forming a word line to couple to a gate of the transistor.   
     
     
         17 . The method of  claim 16 , further comprising forming a metal line in at least a second conductive layer, wherein the second conductive layer is between the first conductive layer and the transistor. 
     
     
         18 . The method of  claim 16 , further comprising forming a third fuse in a second conductive layer, wherein the second conductive layer is between the first conductive layer and the transistor. 
     
     
         19 . The method of  claim 18 , wherein the third fuse is connected to the first fuse or the second fuse in series. 
     
     
         20 . The method of  claim 16 , further comprising forming a metal line in at least a third conductive layer, wherein the third conductive layer is over the first conductive layer.