Imaging device and electronic device

Abstract

An imaging device that facilitates pooling processing. A pixel region includes a plurality of pooling modules and an output circuit, the pooling module includes a pooling circuit and a comparison module, the pooling circuit includes a plurality of pixels and an arithmetic circuit, and the comparison module includes a plurality of comparison circuits and a determination circuit. The pixel can obtain a first signal through photoelectric conversion, and can multiply the first signal by a given scaling factor to generate a second signal. The pooling circuit adds a plurality of second signals in the arithmetic circuit to generate a third signal, the comparison module compares a plurality of third signals and outputs the largest third signal to the determination circuit, and the determination circuit determines the largest third signal and binarizes it to generate a fourth signal. In the imaging device, the pooling module performs pooling processing in accordance with the number of pixels and outputs data obtained by the pooling processing.

1 . An imaging device comprising:
 a pixel region; and   a first circuit,   wherein the pixel region comprises a pooling module and an output circuit,   wherein the pooling module comprises a plurality of pooling circuits and a comparison module,   wherein the pooling circuit comprises a plurality of pixels and an arithmetic circuit, wherein the comparison module comprises a plurality of comparison circuits and a determination circuit,   wherein the pixel is configured to obtain a first signal through photoelectric conversion,   wherein the pixel is configured to multiply the first signal by a given scaling factor to generate a second signal,   wherein the pooling circuit is configured to add a plurality of the second signals in the arithmetic circuit to generate a third signal,   wherein the comparison module is configured to compare a plurality of the third signals, selecting the largest third signal, and outputting the largest third signal to the determination circuit,   wherein the determination circuit is configured to determine the largest third signal and binarize the largest third signal to generate a fourth signal,   wherein the first circuit controls timing at which the fourth signal is output to the output circuit,   wherein the pooling module performs pooling processing in accordance with the number of the pixels, and   wherein the pooling module outputs the fourth signal generated by the pooling processing.