Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a base layer including a silicon material. A field effect transistor is disposed on a first surface of the base layer. A first insulating interlayer covers the field effect transistor, A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern and a first barrier pattern surrounding a sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern and a second barrier pattern surrounding a sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a base layer including a silicon material, the base layer including a first surface and a second surface opposite to the first surface in a vertical direction;   a field effect transistor disposed on the first surface of the base layer;   a first insulating interlayer covering the field effect transistor;   a buried vertical rail passing through the first insulating interlayer and the base layer, the buried vertical rail including a first metal pattern having a sidewall and a first barrier pattern surrounding the sidewall of the first metal pattern;   a first lower insulating interlayer on the second surface of the base layer; and   a lower contact plug passing through the first lower insulating interlayer and directly contacting a lower surface of the buried vertical rail, the lower contact plug including a second metal pattern having a sidewall and a second barrier pattern surrounding the sidewall of the second metal pattern,   wherein a bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a second lower insulating interlayer on a lower surface of the first lower insulating interlayer; and   a lower wiring disposed in the second lower insulating interlayer, the lower wiring is electrically connected to the lower contact plug.   
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a second insulating interlayer on the first insulating interlayer; and   an upper wiring disposed in the second insulating interlayer, the upper wiring is electrically connected to a portion of the field effect transistor.   
     
     
         4 . The semiconductor device of  claim 1 , wherein an interface between the buried vertical rail and the lower contact plug is not coplanar with the second surface of the base layer, the buried vertical rail and the lower contact plug directly contacting each other at the interface. 
     
     
         5 . The semiconductor device of  claim 1 , wherein each of the first and second barrier patterns includes Ti, Ta, TiN, TaN or a combination thereof. 
     
     
         6 . The semiconductor device of  claim 1 , wherein each of the first and second metal patterns includes Cu, W, Mo, Ru, or Nb. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising an insulation liner between the buried vertical rail and the base layer,
 wherein the insulation liner surrounds an outer wall of the buried vertical rail.   
     
     
         8 . The semiconductor device of  claim 1 , wherein:
 the buried vertical rail has a sidewall slope having an inner width that gradually decreases from a top portion of the buried vertical rail to a bottom portion of the buried vertical rail; and   the lower contact plug has a sidewall slope having an inner width that gradually decreases from a bottom portion of the lower contact plug to a top portion of the lower contact plug.   
     
     
         9 . The semiconductor device of  claim 1 , wherein the field effect transistor includes a fin field effect transistor or a multi-bridge channel field effect transistor. 
     
     
         10 . The semiconductor device of  claim 1 , wherein:
 the field effect transistor includes a gate structure and impurity regions; and   a first contact plug electrically connects the buried vertical rail and the impurity regions.   
     
     
         11 . A semiconductor device, comprising:
 a base layer including a silicon material, the base layer including a first surface and a second surface opposite to the first surface in a vertical direction;   active fins protruding from the first surface of the base layer in the vertical direction, the active fins extending in a first direction;   a gate structure on the first surface of the base layer, the gate structure extending in a second direction perpendicular to the first direction and crossing the active fins;   semiconductor patterns on active fins adjacent to both sides of the gate structure, the semiconductor patterns including impurity regions;   a first insulating interlayer on the first surface of the base layer, the first insulating interlayer covering the gate structure and the semiconductor patterns;   a buried vertical rail passing through the first insulating interlayer and the base layer in the vertical direction, the buried vertical rail including a first metal pattern having a sidewall and a first barrier pattern surrounding the sidewall of the first metal pattern;   a first lower insulating interlayer on the second surface of the base layer; and   a lower contact plug passing through the first lower insulating interlayer in the vertical direction and directly contacting a lower surface of the buried vertical rail, the lower contact plug including a second metal pattern having a sidewall and a second barrier pattern surrounding the sidewall of the second metal pattern,   wherein a bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.   
     
     
         12 . The semiconductor device of  claim 11 , further comprising a first contact plug on the first insulating interlayer, the first contact plug electrically connecting the buried vertical rail and the semiconductor patterns to each other. 
     
     
         13 . The semiconductor device of  claim 11 , wherein a bottom surface of the first metal pattern and an upper surface of the second metal pattern are aligned with each other in the vertical direction. 
     
     
         14 . The semiconductor device of  claim 11 , wherein:
 the buried vertical rail has a sidewall slope having an inner width that gradually decreases from a top portion of the buried vertical rail to a bottom portion of the buried vertical rail; and   the first lower contact plug has a sidewall slope having an inner width that gradually decreases from a bottom portion of the first lower contact plug to a top portion of the first lower contact plug.   
     
     
         15 . The semiconductor device of  claim 11 , further comprising:
 a second lower insulating interlayer on a lower surface of the first lower insulating interlayer; and   a lower wiring disposed in the second lower insulating interlayer, the lower wiring is electrically connected to the lower contact plug.   
     
     
         16 . The semiconductor device of  claim 11 , further comprising an insulation liner between the buried vertical rail and the base layer,
 wherein the insulation liner surrounds an outer wall of the buried vertical rail.   
     
     
         17 . The semiconductor device of  claim 11 , wherein the gate structure covers sidewalls and upper surfaces of the active fins. 
     
     
         18 . A method for manufacturing a semiconductor device, comprising:
 forming a field effect transistor on a first surface of a substrate;   forming a first insulating interlayer covering the field effect transistor;   forming a preliminary buried vertical rail extending through the first insulating interlayer to an upper portion of the substrate, the preliminary buried vertical rail including a first metal pattern having a sidewall and a bottom and a first preliminary barrier pattern surrounding the sidewall and the bottom of the first metal pattern;   removing a second surface of the substrate that is opposite to the first surface to expose a lower surface of the first preliminary barrier pattern to form a base layer;   forming a first lower insulating interlayer on a lower surface of the base layer;   forming a first hole passing through the first lower insulating interlayer and exposing the first preliminary barrier pattern of the preliminary buried vertical rail;   forming a buried vertical rail including a first barrier pattern and the first metal pattern by etching the first preliminary barrier pattern exposed by the first hole to form the first barrier pattern;   forming a second barrier layer on a sidewall of the first hole and a bottom of the buried vertical rail;   etching the second barrier layer on a lower surface of the buried vertical rail to form a second barrier pattern on the sidewall of the first hole;   forming a second metal pattern filling the first hole and directly contacting the first metal pattern on the second barrier pattern to form a lower contact plug including the second metal pattern having a sidewall and the second barrier pattern surrounding the sidewall of the second metal pattern.   
     
     
         19 . The method of  claim 18 , wherein the etching of the first preliminary barrier pattern to form the first barrier pattern includes an inductively coupled plasma etching process. 
     
     
         20 . The method of  claim 18 , wherein the etching of the second barrier pattern to form the second barrier pattern includes an inductively coupled plasma etching process.