Coprocessor Register Renaming

Abstract

A coprocessor with register renaming is disclosed. An apparatus includes a plurality of processors and a coprocessor respectively configured to execute processor instructions and coprocessor instructions. The coprocessor receives coprocessor instructions from ones of the processors. The coprocessor includes an array of processing elements and a result register set comprising storage elements respectively distributed within the array of processing elements. For a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member. The result register set implements a plurality of contexts to store respective coprocessor states corresponding to coprocessor instructions received from different processors. Based on a determination that one of the contexts is inactive, the coprocessor is configured to store coprocessor instruction results corresponding to an active context within storage elements of the result register set corresponding to the inactive context.

1 - 20 . (canceled) 
     
     
         21 . An apparatus comprising:
 a plurality of processors configured to execute processor instructions;   a coprocessor configured to decode and execute coprocessor instructions, wherein ones of the plurality of processors are configured to provide the coprocessor instructions to the coprocessor, and wherein the coprocessor includes:
 an operand register set configured to store operands for coprocessor instructions to be executed; 
 an array of processing elements; and 
 a result register set comprising storage elements respectively distributed within the array of processing elements, wherein for a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member; 
 wherein the result register set implements a plurality of contexts configured to store respective coprocessor states corresponding to coprocessor instructions received from different ones of the plurality of processors, the plurality of contexts including a first context reserved for results from a first one of the plurality of processors and a second context reserved for a second one of the plurality of processors; and 
 wherein, based on a determination that the second context is inactive, the coprocessor is configured to store coprocessor instructions results corresponding to the first context within storage elements corresponding the second context. 
   
     
     
         22 . The apparatus of  claim 21 , further comprising register rename logic, wherein the register rename logic is configured to determine that the storage elements corresponding to the second context are unavailable to the first context when the second context is active. 
     
     
         23 . The apparatus of  claim 22 , wherein the register rename logic is configured to:
 determine whether any of the plurality of contexts is inactive; and   assign, in response to determining that at least one of the plurality of contexts is inactive, storage elements of at least one inactive one of the plurality of contexts to an active one of the plurality of contexts.   
     
     
         24 . The apparatus of  claim 21 , wherein the array of elements comprises N rows and N columns of processing elements, wherein N is an integer value. 
     
     
         25 . The apparatus of  claim 21 , wherein the coprocessor is configured to:
 execute a first coprocessor instruction;   store results of executing the first coprocessor instruction in storage elements corresponding to the first context; and   begin execution of a second coprocessor instruction prior to completing storing of the results of executing the first coprocessor instruction, wherein results of the second coprocessor instruction are stored storage elements corresponding to the second context, wherein the second coprocessor instruction is associated with the first context.   
     
     
         26 . The apparatus of  claim 25 , wherein the coprocessor is configured to begin, prior to completing storing of results of the second coprocessor instruction in the storage elements of the second context, a store operation to write back results of executing the first coprocessor instruction from the storage elements of the first context to a system memory. 
     
     
         27 . The apparatus of  claim 21 , wherein the operand register set includes:
 a first operand register configured to store a first vector; and   a second operand register configured to store a second vector;   wherein the coprocessor is configured to use the first and second vectors during execution of at least one coprocessor instruction.   
     
     
         28 . The apparatus of  claim 21 , The apparatus of  claim 21 , wherein the array of processing elements comprises N rows and N columns of processing elements, wherein N is an integer value. 
     
     
         29 . The apparatus of  claim 28 , wherein the coprocessor is configured to:
 execute matrix instructions that use at least a subset of the array of processing elements; and   execute vector instructions that use at lease a subset of the array of processing elements.   
     
     
         30 . The apparatus of  claim 21 , wherein ones of the array of processing elements are configured to execute a clear instruction that writes all logic zeros to corresponding storage elements of the results register set, and wherein, in response to execution of the clear instruction, register rename logic in the coprocessor is configured to determine that a corresponding one of the plurality of contexts is inactive. 
     
     
         31 . A method comprising:
 executing, using ones of a plurality of processors, processor instructions;   executing, using ones of an array of processor elements in a coprocessor, coprocessor instructions provided to the coprocessor from ones of the plurality of processors;   storing, in an operand register set, operands for coprocessor instructions to be executed;   storing coprocessor instruction results for ones of the array of processing elements in corresponding results registers of a results register set, wherein a given one of the results registers is associated with a given one of the array of processing elements such that coprocessor results generated by the given one of the array of processing elements are stored in the given one of the results registers;   implementing, using the results register set, a plurality of contexts to store respective coprocessor states corresponding to coprocessor instructions received from different ones of the plurality of processors, wherein the plurality of contexts include a first context reserved for results from a first one of the plurality of processors and a second context reserved for a second one of the plurality of processors;   determining, using rename logic circuitry, that the second context is inactive; and   storing, based on the determining, coprocessor instruction results corresponding to the first context in storage elements corresponding to the second context.   
     
     
         32 . The method of  claim 31 , further comprising determining, using the rename logic, that the storage elements corresponding to the second context are unavailable to store coprocessor instruction results corresponding to the first context when the second context is active. 
     
     
         33 . The method of  claim 31 , further comprising:
 determining, using the rename logic, whether any of the plurality of contexts is inactive; and   assigning, in response to determining that at least one of the plurality of contexts is inactive, storage elements of at least one inactive one of the plurality of contexts to an active one of the plurality of contexts.   
     
     
         34 . The method of  claim 31 , wherein the array of processing elements comprises N rows and N columns of processing elements, wherein N is an integer value, and wherein the method further comprises executing coprocessor instructions that use at least a subset of the array of processing elements. 
     
     
         35 . The method of  claim 31 , further comprising:
 executing, using the coprocessor, a first coprocessor instruction;   storing results of executing the first coprocessor instruction in storage elements corresponding to the first context;   beginning execution of a second coprocessor instruction, using the coprocessor, prior to completing storing of the results of executing the first coprocessor instruction, wherein the second coprocessor instruction is associated with the first context; and   storing results of the execution of the second coprocessor instruction in storage elements corresponding to the second context.   
     
     
         36 . The method of  claim 35 , further comprising beginning, by the coprocessor and prior to completing storing results of the second coprocessor instruction, a store operation to write back results of executing the first coprocessor instruction from the storage elements corresponding to the first context to a system memory. 
     
     
         37 . A system comprising:
 a plurality of processor cores configured to execute processor instructions;   a coprocessor configured to execute coprocessor instructions, wherein the coprocessor includes:
 an operand register set configured to store operands for coprocessor instructions; 
 an array of processing elements configured to execute coprocessor instructions; and 
 a result register set comprising storage elements respectively distributed within the array of processing elements, wherein for a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member; 
 wherein the result register set implement a plurality of contexts, wherein a given one of the plurality of contexts is reserved for storing results from execution of coprocessor instructions received from a corresponding one of the plurality of processors, wherein the plurality of contexts includes first and second contexts reserved for results from coprocessor instruction received from first and second ones of the plurality of processors, respectively; and 
   register rename logic configured to determine which of the plurality of contexts, if any, is active, and further configured to, based on a determination that the second context is inactive, cause the coprocessor to store coprocessor instructions results corresponding to the first context within storage elements corresponding the second context.   
     
     
         38 . The system of  claim 37 , wherein the register rename logic is further configured to:
 determine whether any of the plurality of contexts is inactive;   determine that the storage elements corresponding to the second context are unavailable to store coprocessor instruction results for the first context when the second context is active; and   assign, in response to determining that at least one of the plurality of contexts is inactive, storage elements of at least one inactive one of the plurality of contexts to an active one of the plurality of contexts.   
     
     
         39 . The system of  claim 37 , wherein the coprocessor is further configured to:
 execute a first coprocessor instruction;   store results of executing the first coprocessor instruction in storage elements corresponding to the first context; and   begin execution of a second coprocessor instruction prior to completing storing of the results of executing the first coprocessor instruction, wherein results of the second coprocessor instruction are stored storage elements corresponding to the second context, wherein the second coprocessor instruction is associated with the first context.   
     
     
         40 . The system of  claim 39 , wherein the coprocessor is configured to begin, prior to completing storing of results of the second coprocessor instruction in the storage elements of the second context, a store operation to write back results of executing the first coprocessor instruction from the storage elements of the first context to a system memory.