Ferroelectric tunnel junction device

Abstract

A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

What is claimed is: 
     
         1 . A ferromagnetic tunnel junction (FTJ) device comprising:
 a heating structure formed around an FJT structure on a plurality of sides;   the FJT structure comprising a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level;   wherein the switching barrier comprises ferroelectric (Fe) material that may be polarized to store information.   
     
     
         2 . The FJT device of  claim 1 , wherein the heating structure and the FJT structure are formed in a BEOL (back-end-of-line) process. 
     
     
         3 . The FJT device of  claim 1 , wherein the switching barrier comprises an Fe material plus an interfacial layer (IL) material. 
     
     
         4 . The FJT device of  claim 3 , wherein the Fe material is formed with sub 40 Å thickness. 
     
     
         5 . The FJT device of  claim 3 , wherein the IL material is formed of a non-polar material with sub 20 Å thickness. 
     
     
         6 . The FJT device of  claim 1 , wherein the Fe material of the switching barrier is crystalized by heat emitted from the heating structure responsive to a current flow through the heating structure. 
     
     
         7 . The FJT device of  claim 1 , wherein the switching barrier is formed around parallel sidewalls of the first conductive electrode and along a bottom of the first conductive electrode to sandwich the first conductive electrode. 
     
     
         8 . The FJT device of  claim 7 , wherein the second conductive electrode is formed around parallel sidewalls of the switching barrier and along the bottom of the switching barrier to sandwich the switching barrier. 
     
     
         9 . A semiconductor fabrication method comprising:
 forming a first conductive electrode over an interconnection structure, the first conductive electrode having sidewalls that extend vertically to a first elevation;   forming a switching barrier within a gap in the first conductive electrode, the switching barrier having sidewalls that extend vertically to the first elevation, the switching barrier comprising ferroelectric material (Fe);   forming a second conductive electrode within a gap in the switching barrier, the second conductive electrode having sidewalls that extend vertically to the first elevation; and   heating the Fe material using a heater structure formed around a plurality of sides of the first conductive electrode to crystalize the Fe material, wherein the crystalized Fe material may be polarized to store information.   
     
     
         10 . The method of  claim 9 , further comprising forming the heater structure, the first conductive electrode, the switching barrier, the second conductive electrode, and the heater structure in a BEOL (back-end-of-line) process. 
     
     
         11 . The method of  claim 9 , wherein the switching barrier comprises an Fe material plus an interfacial layer (IL) material. 
     
     
         12 . The method of  claim 11 , wherein the Fe material is formed with sub 40 Å thickness. 
     
     
         13 . The method of  claim 12 , wherein the IL material is formed of a non-polar material with sub 20 Å thickness. 
     
     
         14 . The method of  claim 9 , wherein the Fe material of the switching barrier is crystalized by heat emitted from the heating structure responsive to a current flow through the heating structure. 
     
     
         15 . The method of  claim 9 , further comprising forming shallow trench isolation (STI) between the heating structure and the first conductive electrode. 
     
     
         16 . A memory device comprising:
 a transistor device;   a memory cell electrically coupled to a source or drain of the transistor device, the memory cell comprising an FJT structure;   a heating structure formed around the memory cell on a plurality of sides; and   the FJT structure comprising a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level;   wherein the switching barrier comprises ferroelectric (Fe) material that may be polarized to store information.   
     
     
         17 . The memory device of  claim 16 , wherein the heating structure and the FJT structure are formed in a BEOL (back-end-of-line) process. 
     
     
         18 . The memory device of  claim 16 , wherein:
 the switching barrier comprises an Fe material plus an interfacial layer (IL) material;   the Fe material is formed with sub 40 Å thickness; and   the IL material is formed of a non-polar material with sub 20 Å thickness.   
     
     
         19 . The memory device of  claim 16 , wherein the Fe material of the switching barrier is crystalized by heat emitted from the heating structure responsive to a current flow through the heating structure. 
     
     
         20 . The memory device of  claim 16 , wherein:
 the switching barrier is formed around parallel sidewalls of the first conductive electrode and along a bottom of the first conductive electrode to sandwich the first conductive electrode; and   the second conductive electrode is formed around parallel sidewalls of the switching barrier and along the bottom of the switching barrier to sandwich the switching barrier.