High Gain Detector Techniques for High Bandwidth Low Noise Phase-Locked Loops

Abstract

In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.

What is claimed is: 
     
         1 . An apparatus comprising:
 a phase measurement circuit including:
 a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input; 
 a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input; 
 a first capacitor coupled between the power terminal and the phase measurement output; 
 a second capacitor coupled between the phase measurement output and a ground terminal; and 
 a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output. 
   
     
     
         2 . The apparatus of  claim 1 , further comprising a pulse generator having a first clock input, a second clock input, an up output, and a down output input, the up input coupled to the up output, and the down input coupled to the down output. 
     
     
         3 . The apparatus of  claim 1 , wherein the charge pump circuit includes:
 a first inverter having a first inverter input and a first inverter output, the first inverter input coupled to the up input;   a third capacitor coupled between the first inverter output and the phase measurement output;   a second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the down input; and   a fourth capacitor coupled between the second inverter output and the phase measurement output.   
     
     
         4 . The apparatus of  claim 1 , wherein the phase measurement circuit includes a first resistor coupled between the first switch and the phase measurement output and a second resistor coupled between the second switch and the phase measurement output. 
     
     
         5 . The apparatus of  claim 1 , wherein the phase measurement circuit includes:
 a third switch coupled between the first and second switches, the third switch having a third switch control terminal coupled to a first pulse input;   a fourth switch coupled between the first switch and the phase measurement output, the fourth switch having a fourth switch control terminal coupled to a second pulse input; and   a fifth switch coupled between the second switch and the phase measurement output, the fifth switch having a fifth switch control terminal coupled to the second pulse input.   
     
     
         6 . The apparatus of  claim 5 , wherein the first and second pulse inputs are coupled to a same pulse input. 
     
     
         7 . The apparatus of  claim 5 , further comprising a control circuit coupled to the first and second pulse inputs, wherein the control circuit is configured to close the third switch before closing the fourth and fifth switches. 
     
     
         8 . The apparatus of  claim 1 , wherein the charge measurement circuit includes:
 a third capacitor coupled to the charge pump output;   a resistor coupled between the charge pump output and the phase measurement output; and   a fourth capacitor coupled between the phase measurement output and the ground terminal.   
     
     
         9 . An apparatus comprising:
 a first phase measurement circuit having a first up input, a first down input, and a first measurement output;   a second phase measurement circuit having a second up input, a second down input, and a second output, the second up input coupled to the first down input, and the second down input coupled to the first up input; and   an amplifier having a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input coupled to the first measurement output, the second amplifier input coupled to the second measurement output, and the amplifier output coupled to a phase measurement output.   
     
     
         10 . The apparatus of  claim 9 , wherein the first phase measurement circuit includes a first charge pump circuit coupled between the first up input, the first down input, and the first measurement output; and
 wherein the second phase measurement circuit includes a second charge pump circuit coupled between the second up input, the second down input, and the second measurement output.   
     
     
         11 . The apparatus of  claim 9 , further comprising a first resistor-capacitor network coupled between the first measurement output and the first amplifier input, and a second resistor-capacitor network coupled between the second measurement output and the second amplifier input. 
     
     
         12 . The apparatus of  claim 9 , further comprising a resistor and a capacitor coupled between the first amplifier input and the amplifier output. 
     
     
         13 . The apparatus of  claim 9 , further comprising a third phase measurement circuit having a third up input, a third down input, and a third measurement output, the third up input coupled to the first down input, the third down input coupled to the first up input, and the third measurement output coupled to the phase measurement output. 
     
     
         14 . The apparatus of  claim 13 , further comprising:
 a resistor-capacitor network coupled between the third measurement output and the phase measurement output; and   a resistor coupled between the amplifier output and the phase measurement output.   
     
     
         15 . The apparatus of  claim 9 , further comprising a first switch coupled between a first voltage source and the first amplifier input and a second switch coupled between a second voltage source and the second amplifier input, the first switch having a first switch control terminal coupled to a low frequency indication input, and the second switch having a second switch control terminal coupled to a high frequency indication input. 
     
     
         16 . The apparatus of  claim 9 , wherein the first amplifier input is a negative amplifier input, and the second amplifier input is a positive amplifier input. 
     
     
         17 . An apparatus comprising:
 a first phase detector circuit having a first reference clock input, a first clock measurement input, and a first phase detector output;   a second phase detector circuit having a second reference clock input, a second clock measurement input, and a second phase detector output, the second reference clock input coupled to the first reference clock input, and the second clock measurement input coupled to the first clock measurement input;   an amplifier having a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input coupled to the first phase detector output, the second amplifier input coupled to the second phase detector output, and the amplifier output coupled to a phase measurement output; and   a resistor and a capacitor coupled between the first amplifier input and the amplifier output.   
     
     
         18 . The apparatus of  claim 17 , wherein each of the first and second phase detectors includes an XOR gate. 
     
     
         19 . The apparatus of  claim 17 , further comprising a first resistor-capacitor network coupled between the first phase detector output and the first amplifier input, and a second resistor-capacitor network coupled between the second phase detector output and the second amplifier input. 
     
     
         20 . The apparatus of  claim 17 , further comprising a first switch coupled between a first voltage source and the first amplifier input and a second switch coupled between a second voltage source and the second amplifier input, the first switch having a first switch control terminal coupled to a low frequency indication input, and the second switch having a second switch control terminal coupled to a high frequency indication input.