Semiconductor Package and Method

Abstract

A method includes directly bonding a first wafer to a second wafer, wherein the bonding electrically connects a first interconnect structure of the first wafer to a second interconnect structure of the second wafer; directly bonding first semiconductor devices to the second wafer, wherein the bonding electrically connects the first semiconductor devices to the second interconnect structure; encapsulating the first semiconductor devices with a first encapsulant; and forming solder bumps over the first semiconductor devices.

What is claimed is: 
     
         1 . A method comprising:
 directly bonding a first wafer to a second wafer, wherein the bonding electrically connects a first interconnect structure of the first wafer to a second interconnect structure of the second wafer;   directly bonding a plurality of first semiconductor devices to the second wafer, wherein the bonding electrically connects the plurality of first semiconductor devices to the second interconnect structure;   encapsulating the plurality of first semiconductor devices with a first encapsulant; and   forming solder bumps over the plurality of first semiconductor devices.   
     
     
         2 . The method of  claim 1 , wherein directly bonding the first wafer to the second wafer comprises dielectric-to-dielectric bonding and metal-to-metal bonding. 
     
     
         3 . The method of  claim 1 , wherein sidewalls of the second wafer are free of the first encapsulant. 
     
     
         4 . The method of  claim 1  further comprising performing a singulation process between two neighboring first semiconductor devices of the plurality of first semiconductor devices. 
     
     
         5 . The method of  claim 1 , wherein directly bonding the plurality of first semiconductor devices to the second wafer comprises forming a first bonding layer and first bonding pads on the second wafer and directly bonding the plurality of first semiconductor devices to the first bonding layer and the first bonding pads. 
     
     
         6 . The method of  claim 1  further comprising directly bonding a third wafer to the first wafer, wherein the bonding electrically connects a third interconnect structure of the first wafer to the first interconnect structure of the first wafer. 
     
     
         7 . The method of  claim 1  further comprising, after directly bonding the first wafer to the second wafer, forming through substrate vias in the second wafer, wherein the through substrate vias extend from an outer surface of the second wafer to the second interconnect structure of the second wafer. 
     
     
         8 . The method of  claim 1  further comprising:
 after directly bonding the plurality of first semiconductor devices to the second wafer, forming through vias in the first semiconductor devices of the plurality of first semiconductor devices; and 
 forming a second bonding layer and second bonding pads on the plurality of first semiconductor devices. 
 
     
     
         9 . The method of  claim 8  further comprising:
 directly bonding a plurality of second semiconductor devices to the second bonding layer and the second bonding pads; and 
 encapsulating the plurality of second semiconductor devices with a second encapsulant. 
 
     
     
         10 . The method of  claim 8  further comprising directly bonding a fourth wafer to the second bonding layer and the second bonding pads. 
     
     
         11 . A method comprising:
 forming first bonding pads on a first side of a first semiconductor substrate;   forming second bonding pads on a first side of a second semiconductor substrate;   bonding the first bonding pads to the second bonding pads using a first metal-to-metal bonding process;   after performing the first metal-to-metal bonding process, forming first through vias in the first semiconductor substrate;   forming third bonding pads on a second side of the first semiconductor substrate, wherein the third bonding pads are electrically connected to the first through vias;   bonding a semiconductor die to the third bonding pads using a second metal-to-metal bonding process;   after performing the second metal-to-metal bonding process, surrounding the semiconductor die with an encapsulant; and   forming second through vias in the semiconductor die.   
     
     
         12 . The method of  claim 11  further comprising, before performing the first metal-to-metal bonding process, performing a first trimming process on sidewalls of the first semiconductor substrate. 
     
     
         13 . The method of  claim 11  further comprising forming integrated circuits in the first semiconductor substrate. 
     
     
         14 . The method of  claim 11  further comprising, after surrounding the semiconductor die with the encapsulant, performing a second trimming process to remove encapsulant from sidewalls of the first semiconductor substrate. 
     
     
         15 . The method of  claim 11  further comprising forming solder bumps on the semiconductor die. 
     
     
         16 . The method of  claim 11 , wherein the first semiconductor substrate is a silicon wafer. 
     
     
         17 . A package comprising:
 a first wafer comprising a first interconnect structure on a first semiconductor substrate;   a plurality of first semiconductor devices directly bonded to the first interconnect structure, wherein each first semiconductor device comprises a through via;   an encapsulant surrounding each first semiconductor device of the plurality of first semiconductor devices;   a first bonding layer extending over the encapsulant and the plurality of first semiconductor devices;   a plurality of first bonding pads in the first bonding layer, wherein each first bonding pad physically and electrically contacts a respective through via of a first semiconductor device; and   a second wafer comprising a second interconnect structure on a second semiconductor substrate, wherein the second interconnect structure is directly bonded to the first bonding layer and the plurality of first bonding pads.   
     
     
         18 . The package of  claim 17 , wherein sidewalls of the second wafer are free of the encapsulant. 
     
     
         19 . The package of  claim 17  further comprising:
 a plurality of through substrate vias in the second semiconductor substrate; 
 a second bonding layer extending over the second semiconductor substrate; and 
 a plurality of second bonding pads in the second bonding layer, wherein each second bonding pad physically and electrically contacts a respective through substrate via. 
 
     
     
         20 . The package of  claim 19  further comprising a plurality of second semiconductor devices directly bonded to the second bonding layer and the plurality of second bonding pads.