Three-dimensional memory devices having through array contacts and methods for forming the same

Abstract

In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a stack structure over the substrate and comprising interleaved conductive layers and dielectric layers; and   a connection structure extending through the stack structure into the substrate,   wherein the connection structure comprises a conductor layer and a spacer over a sidewall of the conductor layer, the conductor layer of the connection structure being in direct contact with the substrate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the spacer comprises a first portion and a second portion arranged in a vertical direction, a first dimension of the first portion in a lateral direction is greater than a second dimension of the second portion in the lateral direction, and the lateral direction is perpendicular to the vertical direction. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the connection structure has a circular shape in a plan view. 
     
     
         4 . The semiconductor device of  claim 1 , wherein edges of the conductive layers and edges of the dielectric layers along a sidewall of the connection structure are aligned. 
     
     
         5 . The semiconductor device of  claim 2 , wherein the stack structure comprises:
 a lower deck; and   an upper deck above the lower deck.   
     
     
         6 . The semiconductor device of  claim 5 , further comprising:
 a channel structure extending through the stack structure,   wherein the channel structure comprises:
 a lower channel structure extending through the lower deck; and 
 an upper channel structure extending through the upper deck. 
   
     
     
         7 . The semiconductor device of  claim 5 , wherein the first portion is located at a junction of the lower deck and the upper deck. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a peripheral device, wherein the connection structure is in contact with the peripheral device.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a slit structure extending vertically through the interleaved conductive layers and dielectric layers in the stack structure and configured to separate the stack structure into a plurality of zones.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the slit structure comprises a dielectric spacer in contact with the conductive layers and the dielectric layers; wherein the dielectric spacer comprises a third portion and a fourth portion arranged in a vertical direction, a third dimension of the third portion in a lateral direction is greater than a fourth dimension of the fourth portion in the lateral direction, and the lateral direction is perpendicular to the vertical direction. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the spacer of the connection structure and the dielectric spacer of the slit structure comprise silicon oxide. 
     
     
         12 . A semiconductor device, comprising:
 a substrate;   a stack structure over the substrate and comprising interleaved conductive layers and dielectric layers; and   a connection structure extending through the stack structure into a substrate,   wherein:   the connection structure has a circular shape in a plan view;   the connection structure comprises a conductor layer and a spacer over a sidewall of the conductor layer; and   the connection structure is configured to provide an interconnect between the stack structure and a peripheral device.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the spacer comprises a first portion and a second portion arranged in a vertical direction, a first dimension of the first portion in a lateral direction is greater than a second dimension of the second portion in the lateral direction, and the lateral direction is perpendicular to the vertical direction. 
     
     
         14 . The semiconductor device of  claim 12 , wherein edges of the conductive layers and edges of the dielectric layers along a sidewall of the connection structure are aligned. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the stack structure comprises:
 a lower deck; and   an upper deck above the lower deck.   
     
     
         16 . The semiconductor device of  claim 15 , further comprising:
 a channel structure extending through the stack structure,   wherein the channel structure comprises:
 a lower channel structure extending through the lower deck; and 
 an upper channel structure extending through the upper deck. 
   
     
     
         17 . The semiconductor device of  claim 15 , wherein the first portion is located at a junction of the lower deck and the upper deck. 
     
     
         18 . The semiconductor device of  claim 12 , further comprising:
 a slit structure extending vertically through the interleaved conductive layers and dielectric layers in the stack structure and configured to separate the stack structure into a plurality of zones.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the slit structure comprises a dielectric spacer in contact with the conductive layers and the dielectric layers; wherein the dielectric spacer comprises a third portion and a fourth portion arranged in a vertical direction, a third dimension of the third portion in a lateral direction is greater than a fourth dimension of the fourth portion in the lateral direction, and the lateral direction is perpendicular to the vertical direction. 
     
     
         20 . The semiconductor device of  claim 19 , wherein the spacer of the connection structure and the dielectric spacer of the slit structure comprise silicon oxide.