Semiconductor device and manufacturing method thereof

Abstract

It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a gate electrode layer over a substrate;   an oxide insulating film over the gate electrode layer;   an oxide semiconductor layer over the oxide insulating film, the oxide semiconductor layer comprising a channel formation region of a transistor;   a source electrode layer and a drain electrode layer over and in contact with the oxide semiconductor layer;   a first insulating layer over and in contact with the oxide semiconductor layer;   a first wiring layer over the first insulating layer and electrically connected to one of the source electrode layer and the drain electrode layer via a first opening in the first insulating layer;   a second wiring layer over and in contact with the first wiring layer;   a third wiring layer over the first insulating layer and electrically connected to the other of the source electrode layer and the drain electrode layer via a second opening in the first insulating layer;   a fourth wiring layer over and in contact with the third wiring layer; and   a second insulating layer over the second wiring layer and the fourth wiring layer,   wherein a first thickness of the source electrode layer and a second thickness of the drain electrode layer are smaller than a third thickness of the oxide semiconductor layer, and   wherein, in a cross-sectional view, the first wiring layer and the oxide semiconductor layer overlap with each other with the one of the source electrode layer and the drain electrode layer provided therebetween.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the channel formation region of the oxide semiconductor layer comprises a crystalline portion, and   wherein the oxide semiconductor layer comprises indium, gallium, and zinc.   
     
     
         4 . The semiconductor device according to  claim 2 , wherein a grain diameter of a crystalline portion in the channel formation region of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 20 nm. 
     
     
         5 . A semiconductor device comprising:
 a gate electrode layer over a substrate;   an oxide insulating film over the gate electrode layer;   an oxide semiconductor layer over the oxide insulating film, the oxide semiconductor layer comprising a channel formation region of a transistor;   a source electrode layer and a drain electrode layer over and in contact with the oxide semiconductor layer;   a first insulating layer over and in contact with the oxide semiconductor layer;   a first wiring layer over the first insulating layer and in contact with one of the source electrode layer and the drain electrode layer via a first opening in the first insulating layer;   a second wiring layer over and in contact with the first wiring layer;   a second insulating layer over the second wiring layer; and   a first pixel electrode layer of a liquid crystal element over the second insulating layer and in contact with the second wiring layer in a second opening in the second insulating layer,   wherein a first thickness of the source electrode layer and a second thickness of the drain electrode layer are smaller than a third thickness of the oxide semiconductor layer,   wherein a combined thickness of the first wiring layer and the second wiring layer is larger than the third thickness of the oxide semiconductor layer, and   wherein, in a cross-sectional view, the second opening comprises a region not overlapping with the first opening.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein the channel formation region of the oxide semiconductor layer comprises a crystalline portion, and   wherein the oxide semiconductor layer comprises indium, gallium, and zinc.   
     
     
         7 . The semiconductor device according to  claim 5 , wherein a grain diameter of a crystalline portion in the channel formation region of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 20 nm. 
     
     
         8 . A semiconductor device comprising:
 a gate electrode layer over a substrate;   an oxide insulating film over the gate electrode layer;   an oxide semiconductor layer over the oxide insulating film, the oxide semiconductor layer comprising a channel formation region of a transistor;   a source electrode layer and a drain electrode layer over and in contact with the oxide semiconductor layer;   a first insulating layer over and in contact with the oxide semiconductor layer;   a first wiring layer over the first insulating layer and in contact with one of the source electrode layer and the drain electrode layer via a first opening in the first insulating layer;   a second wiring layer over and in contact with the first wiring layer;   a second insulating layer over the second wiring layer; and   a first pixel electrode layer of a liquid crystal element over the second insulating layer and in contact with the second wiring layer in a second opening in the second insulating layer,   wherein a first thickness of the source electrode layer and a second thickness of the drain electrode layer are smaller than a third thickness of the oxide semiconductor layer,   wherein a combined thickness of the first wiring layer and the second wiring layer is larger than the third thickness of the oxide semiconductor layer,   wherein, in a cross-sectional view, the second opening comprises a region not overlapping with the first opening,   wherein, in the cross-sectional view, the one of the source electrode layer and the drain electrode layer overlaps with the gate electrode layer, and   wherein the first wiring layer is in contact with a side surface of the oxide semiconductor layer.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the channel formation region of the oxide semiconductor layer comprises a crystalline portion, and   wherein the oxide semiconductor layer comprises indium, gallium, and zinc.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein a grain diameter of a crystalline portion in the channel formation region of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 20 nm.