Protective insulator for hfet devices

Abstract

An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

1 - 20 . (canceled) 
     
     
         21 . A method of fabricating a transistor comprising:
 depositing a semiconductor layer;   depositing a first insulation layer and a first passivation layer to form a first composite passivation layer;   creating a first footprint for an ohmic contact by plasma etching the first composite passivation layer;   forming the ohmic contact;   creating a second footprint for a gate by plasma etching the first composite passivation layer;   forming the gate;   depositing a second insulation layer and a second passivation layer to form a second composite passivation layer; and   creating a third footprint for a field plate by plasma etching the second composite passivation layer.   
     
     
         22 . The method of  claim 21 , wherein forming the ohmic contact comprises:
 forming the ohmic contact by recess etching.   
     
     
         23 . The method of  claim 21 , wherein forming the gate comprises:
 forming the gate by depositing a metal.   
     
     
         24 . The method of  claim 21 , wherein creating the first footprint for the ohmic contact by plasma etching the first composite passivation layer comprises:
 using the first insulation layer as an etch stop.   
     
     
         25 . The method of  claim 21 , wherein creating the third footprint for the field plate by plasma etching the second composite passivation layer comprises:
 using the second insulation layer as an etch stop.   
     
     
         26 . The method of  claim 21 , wherein the semiconductor layer comprises a compound semiconductor. 
     
     
         27 . The method of  claim 21 , wherein the first insulation layer has a larger bandgap than the first passivation layer. 
     
     
         28 . The method of  claim 21 , wherein the second insulation layer has a larger bandgap than the second passivation layer. 
     
     
         29 . The method of  claim 21 , wherein the first insulation layer comprises aluminum oxide. 
     
     
         30 . The method of  claim 21 , wherein the second insulation layer comprises silicon dioxide. 
     
     
         31 . The method of  claim 21 , wherein the first passivation layer and the second passivation layer comprise silicon nitride. 
     
     
         32 . The method of  claim 21 , wherein the field plate is a source field plate. 
     
     
         33 . The method of  claim 21 , wherein the field plate is a gate field plate. 
     
     
         34 . The method of  claim 21 , wherein the first insulation layer is a gate dielectric.