Bga stim package architecture for high performance systems

Abstract

Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a die on a top surface of a package substrate;   an integrated heat spreader (IHS) on the top surface of the package substrate, wherein the IHS has a bottom surface positioned above the die;   a first solder coupling a top surface of the die to the bottom surface of the IHS, the first solder comprising 95% to 99.99% indium solder;   a second solder on a bottom surface of the package substrate, the second solder comprising an alloy including tin (Sn) and bismuth (Bi), wherein the second solder has a weight percentage of the Bi that is greater than approximately 43%; and   a solder ball on the second solder on the bottom surface of the package substrate, wherein the solder ball is in direct physical contact with the second solder.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the bottom surface of the package substrate includes a ball grid array (BGA), and wherein the BGA includes a pad. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the top surface of the die includes a backside metal (BSM) layer, and wherein the BSM layer is between the first solder and the die. 
     
     
         4 . The semiconductor package of  claim 2 , wherein the solder ball is an alloy of Sn, silver (Ag), and copper (Cu) (SAC), and wherein the solder ball is conductively coupled to the pad on the bottom surface of the package substrate. 
     
     
         5 . The semiconductor package of  claim 4 , wherein the package substrate conductively couples the die to the pad, the second solder, and the solder ball. 
     
     
         6 . The semiconductor package of  claim 4 , further comprising:
 an electronic device on the bottom surface of the package substrate;   the second solder on a top surface of a second package substrate; and   an underfill between the bottom surface of the package substrate and the top surface of the second package substrate, wherein the underfill surrounds the second solder, the solder ball, and the electronic device.   
     
     
         7 . The semiconductor package of  claim 6 , wherein the solder ball conductively couples the second solder on the bottom surface of the package substrate to the second solder on the top surface of the second package substrate. 
     
     
         8 . A semiconductor package, comprising:
 a die on a top surface of a package substrate, wherein the package substrate includes an interposer;   an integrated heat spreader (IHS) on the top surface of the package substrate, wherein the IHS has a bottom surface positioned above the die;   a first solder coupling a top surface of the die to the bottom surface of the IHS, the first solder comprising 95% to 99.99% indium solder;   a second solder on a bottom surface of the package substrate, the second solder comprising an alloy including Sn and Bi, wherein the second solder has a weight percentage of the Bi that is between approximately 35% to 58%;   a third solder on and around the second solder and the bottom surface of the package substrate, wherein the third solder includes an epoxy, a flux, and a metal powder; and   a solder ball on the second solder on the bottom surface of the package substrate, wherein the solder ball is in direct physical contact with the second solder and with the third solder.   
     
     
         9 . The semiconductor package of  claim 8 , wherein the bottom surface of the package substrate includes a ball grid array (BGA), and wherein the BGA includes a pad. 
     
     
         10 . The semiconductor package of  claim 8 , wherein the top surface of the die includes a backside metal (BSM) layer, and wherein the BSM layer is between the first solder and the die. 
     
     
         11 . The semiconductor package of  claim 9 , wherein the solder ball is an alloy of Sn, Ag and Cu, and wherein the solder ball is conductively coupled to the pad on the bottom surface of the package substrate. 
     
     
         12 . The semiconductor package of  claim 11 , wherein the package substrate conductively couples the die to the pad, the third solder, the second solder, and the solder ball. 
     
     
         13 . The semiconductor package of  claim 11 , further comprising:
 an electronic device on the bottom surface of the package substrate; and   the second solder on a top surface of a second package substrate, wherein the second package substrate includes a printed circuit board (PCB).   
     
     
         14 . The semiconductor package of  claim 11 , wherein the solder ball conductively couples the second solder and the third solder on the bottom surface of the package substrate to the second solder on the top surface of the second package substrate. 
     
     
         15 . A method of fabricating a semiconductor package, the method comprising:
 providing a die on a top surface of a package substrate;   providing an integrated heat spreader (IHS) on the top surface of the package substrate, wherein the IHS has a bottom surface positioned above the die;   coupling a top surface of the die to the bottom surface of the IHS with a first solder, the first solder comprising 95% to 99.99% indium solder;   forming a second solder on a bottom surface of the package substrate, the second solder comprising an alloy including tin (Sn) and bismuth (Bi), and the second solder having a weight percentage of the Bi that is greater than approximately 43%; and   forming a solder ball on the second solder on the bottom surface of the package substrate, wherein the solder ball is in direct physical contact with the second solder.   
     
     
         16 . The method of  claim 15 , wherein the bottom surface of the package substrate includes a ball grid array (BGA), and wherein the BGA includes a pad. 
     
     
         17 . The method of  claim 15 , wherein the top surface of the die includes a backside metal (BSM) layer, and wherein the BSM layer is between the first solder and the die. 
     
     
         18 . The method of  claim 16 , wherein the solder ball is an alloy of Sn, silver (Ag), and copper (Cu) (SAC), and wherein the solder ball is conductively coupled to the pad on the bottom surface of the package substrate. 
     
     
         19 . The method of  claim 18 , wherein the package substrate conductively couples the die to the pad, the second solder, and the solder ball. 
     
     
         20 . The method of  claim 18 , further comprising:
 providing an electronic device on the bottom surface of the package substrate;   forming the second solder on a top surface of a second package substrate; and   forming an underfill between the bottom surface of the package substrate and the top surface of the second package substrate, wherein the underfill surrounds the second solder, the solder ball, and the electronic device, and wherein the solder ball conductively couples the second solder on the bottom surface of the package substrate to the second solder on the top surface of the second package substrate.