Scan driver for a display device

Abstract

A scan driver for a display device may include a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage may include: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.

What is claimed is: 
     
         1 . A scan driver for a display device comprising:
 a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage,   wherein the first scan stage comprises:   a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line;   a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node;   a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line;   a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node;   a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; and   a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node,   wherein the first node is coupled to a first carry line.