Histogram operation

Abstract

A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

What is claimed is: 
     
         1 . A device comprising:
 a processor core that includes a register configured to store a set of indices; and   a memory coupled to the processor core and configured to store a set of table elements, wherein the processor core is configured to:
 receive an instruction; and 
 based on the instruction, for each index of the set of indices, perform an arithmetic operation on a respective table element of the set of table elements associated with the respective index. 
   
     
     
         2 . The device of  claim 1 , wherein the arithmetic operation is incrementing the respective table element by one. 
     
     
         3 . The device of  claim 1 , wherein:
 the register is a first register;   the processor core includes a second register configured to store a set of weight values; and   the arithmetic operation is incrementing the respective table element by a respective weight value of the set of weight values.   
     
     
         4 . The device of  claim 3 , wherein the instruction specifies the first register, the set of table elements, and the second register. 
     
     
         5 . The device of  claim 4 , wherein the instruction includes:
 a first field that specifies the first register;   a second field that follows the first field and that specifies the set of table elements; and   a third field the follows the second field that specifies the second register.   
     
     
         6 . The device of  claim 1 , wherein the instruction specifies the register and the set of table elements. 
     
     
         7 . The device of  claim 6 , wherein the instruction includes:
 a first field that specifies the register; and   a second field that follows the first field and that specifies the set of table elements.   
     
     
         8 . The device of  claim 6 , wherein:
 the register is a first register;   the processor core includes a second register configured to store a base address associated with the set of table elements; and   the instruction specifies the set of table elements by specifying the second register.   
     
     
         9 . The device of  claim 1 , wherein:
 the register is a first register;   the processor core includes a second register configured to store a configuration associated with the set of table elements; and   the instruction specifies the second register.   
     
     
         10 . The device of  claim 9 , wherein the configuration specifies at least one parameter from a group consisting of: a promotion mode for values of the set of table elements, a table size for the set of table elements, whether to saturate the values of the set of table elements, whether the values of the set of tables are signed, and an element size for the set of table elements. 
     
     
         11 . The device of  claim 1 , wherein the memory is a cache memory. 
     
     
         12 . The device of  claim 11 , wherein the cache memory is a level one (L1) data cache memory. 
     
     
         13 . A method comprising:
 storing a set of table elements in a memory;   storing a set of indices in a register of a processor core;   receiving an instruction, by the processor core; and   based on the instruction, for each index of the set of indices, performing an arithmetic operation on a respective table element of the set of table elements associated with the respective index.   
     
     
         14 . The method of  claim 13 , wherein the arithmetic operation is incrementing the respective table element by one. 
     
     
         15 . The method of  claim 13 , wherein:
 the register is a first register;   the method further comprises storing a set of weight values in a second register of the processor core; and   the arithmetic operation is incrementing the respective table element by a respective weight value of the set of weight values.   
     
     
         16 . The method of  claim 15 , wherein the instruction specifies the first register, the set of table elements, and the second register. 
     
     
         17 . The method of  claim 16 , wherein the instruction includes:
 a first field that specifies the first register;   a second field that follows the first field and that specifies the set of table elements; and   a third field the follows the second field that specifies the second register.   
     
     
         18 . The method of  claim 13 , wherein the instruction specifies the register and the set of table elements. 
     
     
         19 . The method of  claim 18 , wherein the instruction includes:
 a first field that specifies the register; and   a second field that follows the first field and that specifies the set of table elements.   
     
     
         20 . The method of  claim 19 , wherein the memory is a level one (L1) data cache memory.