Efficient logic blocks architectures for dense mapping of multipliers

Abstract

An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.

1 . A logic block implementable on an integrated circuit device, the logic block comprising:
 a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs;   adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;   circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs; and   a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.   
     
     
         2 . The logic block of  claim 1 , further comprising additional circuitry configurable to receive the portion of the plurality of inputs and the sum and determine a second sum of the portion of the plurality of inputs and the sum. 
     
     
         3 . The logic block of  claim 2 , wherein:
 the adding circuitry is configurable to receive a first carry-in value from a second logic block;   the circuitry is configurable to generate a second carry-in value from the second logic block; and   the additional circuitry is configurable to generate a third carry-in value from the second logic block.   
     
     
         4 . The logic block of  claim 1 , wherein the logic block is configurable to:
 generate eight partial products; and   perform signed and unsigned multiplication operations.   
     
     
         5 . The logic block of  claim 1 , wherein the circuitry is configurable to receive an enable/disable signal to disable the circuitry when the circuitry is not used. 
     
     
         6 . The logic block of  claim 1 , wherein:
 a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs; and   the logic block further comprises a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables.   
     
     
         7 . The logic block of  claim 6 , wherein the multiplexer is configurable to:
 receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal; and   provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal.   
     
     
         8 . The logic block of  claim 1 , wherein:
 the first plurality of outputs comprises four partial products generated based on the plurality of inputs; and   the third plurality of outputs comprises two partial products.   
     
     
         9 . The logic block of  claim 8 , wherein the first portion of the third plurality of outputs comprises a first partial product of the two partial products. 
     
     
         10 . The logic block of  claim 9 , further comprising a second adder configurable to determine a second sum of a second portion of the second plurality of outputs and a second partial product of the two partial products. 
     
     
         11 . An integrated circuit device, comprising a logic block, wherein the logic block comprises:
 a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs;   adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;   circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs; and   a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.   
     
     
         12 . The integrated circuit device of  claim 11 , wherein:
 the logic block further comprises additional circuitry configurable to receive the portion of the plurality of inputs and the sum and determine a second sum of the portion of the plurality of inputs and the sum;   the adding circuitry is configurable to receive a first carry-in value from a second logic block;   the circuitry is configurable to generate a second carry-in value from the second logic block; and   the additional circuitry is configurable to generate a third carry-in value from the second logic block.   
     
     
         13 . The integrated circuit device of  claim 11 , further comprising a second adder configurable to determine a second sum of the second plurality of outputs and a second portion of the third plurality of outputs. 
     
     
         14 . The integrated circuit device of  claim 13 , further comprising additional circuitry configurable to receive the portion of the plurality of inputs and the sum and determine a third sum of the portion of the plurality of inputs and the sum. 
     
     
         15 . The integrated circuit device of  claim 11 , wherein:
 a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs; and   the logic block further comprises a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:   receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal; and   provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal.   
     
     
         16 . The integrated circuit device of  claim 15 , wherein:
 the first portion of the plurality of lookup tables is configurable to receive a third bit value, a fourth bit value, and a fifth bit value of the plurality of inputs;   the second portion of the plurality of lookup tables is configurable to receive the third bit value, the fourth bit value, and a sixth bit value of the plurality of inputs; and   the circuitry is configurable to receive the second bit value or the fifth bit value of the plurality of inputs.   
     
     
         17 . The integrated circuit device of  claim 11 , further comprising programmable logic. 
     
     
         18 . A non-transitory computer-readable medium comprising instructions that, when executed, cause a logic block of an integrated circuit device to be configured to perform multiplication operations, wherein the logic block comprises:
 a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs;   adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs;   circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs; and   a first adder configured to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.   
     
     
         19 . The non-transitory computer-readable medium of  claim 18 , wherein:
 a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs; and   the logic block further comprises a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:
 receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal; and 
 provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal. 
   
     
     
         20 . The non-transitory computer-readable medium of  claim 18 , wherein when the instructions are executed by a second integrated circuit device, the logic block of integrated circuit device is configured to perform the multiplication operations.