Memory structure and method of forming the same

Abstract

A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.

What is claimed is: 
     
         1 . A method, comprising:
 providing a substrate;   forming a CMOS (complementary metal-oxide semiconductor) circuitry over the substrate;   forming a first dielectric film over the substrate on the CMOS circuitry, and patterning the first dielectric film using a first mask;   forming bit line conductive layers in first openings defined by the first mask;   forming a second dielectric film over the first dielectric film, and patterning the second dielectric film using a second mask;   forming bit line vias in second openings defined by the second mask, wherein the bit line vias have a staggered arrangement;   forming a memory array on the second dielectric film and electrically connected to the bit line vias;   forming a third dielectric film on the memory array, and patterning the third dielectric film using a third mask; and   forming source line vias in third openings defined by the third mask, wherein the source line vias have a staggered arrangement and are electrically connected to the memory array.   
     
     
         2 . The method according to  claim 1 , further comprising:
 forming a fourth dielectric film over the third dielectric film, and patterning the fourth dielectric film using a fourth mask; and   forming source line conducive layers in fourth openings defined by the fourth mask.   
     
     
         3 . The method according to  claim 2 , further comprising a plurality of connection structures connecting the source line conductive layers to the CMOS circuitry, wherein the plurality of connection structures is located in between a word line stack of the memory array and a word line stack of a dummy array. 
     
     
         4 . The method according to  claim 1 , wherein the bit line vias are non-overlapped with the source line vias. 
     
     
         5 . The method according to  claim 1 , wherein forming the memory array comprises:
 forming a word line stack on the second dielectric film, wherein the word line stack has a first side surface and a second side surface opposite to the first side surface; and   forming source/drain regions on the first side surface and the second side surface, wherein the source/drain regions on the first side surface are staggered from the source/drain regions on the second side surface.   
     
     
         6 . The method according to  claim 5 , further comprising:
 forming channel material layers on the first side surface and the second side surface prior to forming the source/drain regions;   forming dielectric materials on the channel material layers, and patterning the dielectric materials to form dielectric pillars; and   wherein the source/drain regions are formed on two sides of the dielectric pillars.   
     
     
         7 . The method according to  claim 1 , wherein forming the CMOS circuitry further comprises:
 forming an interconnect structure on the substrate prior to forming the first dielectric film, wherein the bit line conductive layers, the bit line vias and the source line vias are electrically connected to the interconnect structure.   
     
     
         8 . A method, comprising:
 forming a CMOS (complementary metal-oxide semiconductor) circuitry over a substrate;   forming a bit line array disposed on and electrically connected to the CMOS circuitry;   forming an active array including memory cells and a dummy array including dummy memory cells over the bit line array, wherein the active array is connected to the bit line array, and the dummy array is disconnected from the bit line array;   forming a source line array disposed on and electrically connected to the active array; and   forming connection structures passing through a periphery of the active array and passing through the bit line array and electrically connected to the CMOS circuitry, wherein the connection structures are sandwiched in between the memory cells of the active array and dummy memory cells of the dummy array.   
     
     
         9 . The method according to  claim 8 , wherein the bit line array comprises a plurality of bit line vias, and the source line array comprises a plurality of source line vias, and wherein the plurality of bit line vias and the plurality of source line vias are arranged in a staggered arrangement. 
     
     
         10 . The method according to  claim 9 , wherein the plurality of bit line vias and the plurality of source line vias are non-overlapped with one another. 
     
     
         11 . The method according to  claim 8 , wherein forming the active array including the memory cells further comprises:
 forming a word line stack having a first side surface and a second side surface opposite to the first side surface;   forming first sets of stacked memory cells along the first side surface; and   forming second sets of stacked memory cells along the second side surface, wherein the first sets of stacked memory cells are staggered from the second sets of stacked memory cells.   
     
     
         12 . The method according to  claim 11 , further comprising forming isolation pillars along the first side surface and along the second side surface of the word line stack, wherein the isolation pillars located on the first side surface are staggered from the isolation pillars located on the second side surface. 
     
     
         13 . The method according to  claim 11 , further comprising:
 forming a second word line stack having a third side surface and a fourth side surface opposite to the third side surface, wherein the third side surface is facing the second side surface of the word line stack, and the second sets of stacked memory cells are further formed along the third side surface of the second word line stack; and   forming a third sets of stacked memory cells along the fourth side surface, wherein the third sets of stacked memory cells are aligned with the first sets of stacked memory cells, and staggered from the second sets of stacked memory cells.   
     
     
         14 . The method according to  claim 8 , wherein the formation of the bit line array is completed by using two masks, and the formation of the source line array is completed by using two masks. 
     
     
         15 . A method, comprising:
 forming a CMOS (complementary metal-oxide semiconductor) circuitry over a substrate;   forming a bit line array disposed on and electrically connected to the CMOS circuitry, wherein forming the bit line array comprises:   patterning a first dielectric film with a first mask to form first openings, and forming a plurality of bit line conductive layers comprising a first bit line conductive layer, a second bit line conductive layer and a third bit line conductive layer in the first openings, wherein the plurality of bit line conductive layers are extending along a first direction and spaced apart from one another in a second direction perpendicular to the first direction, and the second bit line conductive layer is located in between the first bit line conductive layer and the third bit line conductive layer;   patterning a second dielectric film with a second mask to form second openings, and forming a plurality of bit line vias in the second openings, wherein the plurality of bit line vias is directly formed over the first bit line conductive layer, the second bit line conductive layer and the third bit line conductive layer, and wherein the plurality of bit line vias located on the first bit line conductive layer and on the third bit line conductive layer are overlapped with one another along the second direction, and non-overlapped with the plurality of bit line vias located on the second bit line conductive layer; and   forming a memory array on the plurality of bit line vias and forming a dummy array aside the memory array.   
     
     
         16 . The method according to  claim 15 , wherein forming the memory array and the dummy array further comprises forming a plurality of first conductive pillars in the memory array and the dummy array, and the plurality of first conductive pillars in the memory array is electrically connected to the bit line array, and the plurality of first conductive pillars in the dummy array is disconnected from the bit line array. 
     
     
         17 . The method according to  claim 16 , further comprises forming a source line array disposed on the memory array, wherein forming the source line array comprises:
 patterning a third dielectric film with a third mask to form third openings, and forming a plurality of source line vias in the third openings and electrically connected to the memory array; and   patterning a fourth dielectric film with a fourth mask to form fourth openings and forming a plurality of source line conductive layers in the fourth openings, wherein the plurality of source conductive layers is electrically connected to the plurality of source line vias.   
     
     
         18 . The method according to  claim 17 , further comprising a plurality of connection structures electrically connecting the plurality of source conductive layers to the CMOS circuitry, wherein the plurality of connection structures passes through the memory array, and is located in between a word line stack of the memory array and a word line stack of a dummy array. 
     
     
         19 . The method according to  claim 17 , wherein the plurality of source line vias is non-overlapped with the plurality of bit line vias. 
     
     
         20 . The method according to  claim 17 , wherein forming the memory array and the dummy array further comprises forming a plurality of second conductive pillars in the memory array and the dummy array, and the plurality of second conductive pillars in the memory array is electrically connected to the source line array, and the plurality of second conductive pillars in the dummy array is disconnected from the source line array.