Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate, an upper structure, a vertical transistor an electrical pad. The upper structure is disposed on the substrate and defines a hole. The vertical transistor is disposed in the hole. The electrical pad is disposed in the hole and on the vertical transistor. A top surface of the electrical pad is substantially aligned with a topmost surface of the upper structure.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate including a capacitor;   a vertical transistor disposed on the substrate, and electrically connected to the capacitor;   an electrical pad disposed on the vertical transistor, wherein the electrical pad has a consistent thickness; and   a bit line electrically connected to the electrical pad;   wherein a bottom surface of the bit line is substantially aligned with a top surface of the electrical pad;   wherein the capacitor is a ring structure, and an upper portion of the capacitor is exposed from a top surface of the substrate.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the vertical transistor is electrically connected to the capacitor through a conductive material surrounded by a second electrode of the capacitor. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the second electrode of the capacitor is located outside a vertical projection of the vertical transistor. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising:
 a bottom insulation layer disposed on the substrate;   a word line disposed on the bottom insulation layer; and   a top insulation layer disposed on the word line.   
     
     
         5 . The semiconductor structure of  claim 4 , wherein an extension direction of the word line is perpendicular to an extension direction of the bit line. 
     
     
         6 . The semiconductor structure of  claim 4 , wherein, and the vertical transistor extends through the bottom insulation layer and the word line. 
     
     
         7 . The semiconductor structure of  claim 4 , wherein a height of the vertical transistor is greater than a sum of a thickness of the bottom insulation layer and a thickness of the word line, and the top insulation layer has a consistent thickness. 
     
     
         8 . The semiconductor structure of  claim 4 , wherein a sum of a height of the vertical transistor and the thickness of the electrical pad is substantially equal to a sum of a thickness of the bottom insulation layer, a thickness of the word line and a thickness of the top insulation layer. 
     
     
         9 . A method of manufacturing a semiconductor structure, composing:
 providing a stacked structure including a substrate and an upper structure disposed on the substrate;   forming a hole to extend through the upper structure;   forming a vertical transistor in the hole;   forming an electrical pad in the hole and on the vertical transistor; and   forming a conductive structure on the electrical pad, wherein a top corner of the electrical pad is free from damage.   
     
     
         10 . The method of  claim 9 , wherein the substrate includes a capacitor, and the vertical transistor is electrically connected to the capacitor. 
     
     
         11 . The method of  claim 9 , wherein the upper structure includes a bottom insulation layer disposed on the substrate, a conductive layer disposed on the bottom insulation layer and a top insulation layer disposed on the conductive layer. 
     
     
         12 . The method of  claim 9 , wherein after the vertical transistor is formed in the hole, an upper portion of the vertical transistor is removed to form a recess. 
     
     
         13 . The method of  claim 12 , wherein the electrical pad is formed in the recess. 
     
     
         14 . The method of  claim 9 , wherein a top surface of the electrical pad is substantially aligned with a top surface of the upper structure. 
     
     
         15 . The method of  claim 9 , wherein a portion of the conductive structure contacts a top surface of the upper structure, and a bottom surface of the conductive structure is leveled with a top surface of the electrical pad and a top surface of the upper structure.