Bent fin devices

Abstract

Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first fin and a second fin rising from a substrate and extending lengthwise along a first direction; and   a first gate structure wrapping over channel regions of the first fin and the second fin and extending along a second direction perpendicular to the first direction,   wherein the first fin bends away from the second fin along the second direction and the second fin bends away from the first fin along the second direction.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a first isolation feature adjacent to the first fin and away from the second fin;   a second isolation feature disposed between the first fin and the second fin; and   a third isolation feature adjacent to the second fin and away from the first fin,   wherein a top surface of the second isolation feature is lower than top surfaces of the first isolation feature and the third isolation feature.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 a third fin spaced apart from the first fin by the first isolation feature,   wherein a width of the first isolation feature along the second direction is greater than a width of the second isolation feature along the second direction.   
     
     
         4 . The semiconductor device of  claim 3 , further comprising:
 a second gate structure wrapping over a channel region of the third fin.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the first gate structure is insulated from the second gate structure along the second direction by a gate cut feature. 
     
     
         6 . The semiconductor device of  claim 2 ,
 wherein the top surface of the second isolation feature is lower than top surfaces of the first isolation feature and the third isolation feature by a difference between about 3 nm and about 5 nm.   
     
     
         7 . The semiconductor device of  claim 1 , wherein the first fin and the second fin comprise germanium. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first fin and the second fin comprise at least one double-fin device. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a first source/drain feature over a source/drain region of the first fin; and   a second source/drain feature over a source/drain of the second fin,   wherein the first source/drain feature and the second source/drain feature bend away from one another along the second direction.   
     
     
         10 . A semiconductor structure, comprising:
 a substrate comprising a first area and a second area;   a first pair of fins and a second pair of fins over the first area; and   a third pair of fins and a fourth pair of fins over the second area,   wherein a pitch of the first pair of fins and the second pair of fins is the same as a pitch of the third pair of fins and the fourth pair of fins,   wherein the first pair of fins and the second pair of fins rise straight from the first area of the substrate,   wherein fins in the third pair of fins bend away from each other,   wherein fins in the fourth pair of fins bend away from each other.   
     
     
         11 . The semiconductor structure of  claim 10 , further comprising:
 an isolation feature disposed over the substrate,   wherein portions of the isolation feature disposed between the third pair of fins or between the fourth pair of fins is thinner than a portion of the isolation feature between the third pair of fins and the fourth pair of fins.   
     
     
         12 . The semiconductor structure of  claim 10 , further comprising:
 a first gate structure wrapping over the first pair of fins;   a second gate structure wrapping over the second pair of fins;   a third gate structure wrapping over the third pair of fins; and   a fourth gate structure wrapping over the fourth pair of fins.   
     
     
         13 . The semiconductor structure of  claim 12 ,
 Wherein the first gate structure is spaced apart from the second gate structure by a first gate cut feature,   Wherein the third gate structure is spaced apart from the fourth gate structure by a second gate cut feature.   
     
     
         14 . The semiconductor structure of  claim 10 ,
 wherein the first pair of fins comprise a first double-fin device,   wherein the third pair of fins comprise a second double-fin device.   
     
     
         15 . The semiconductor structure of  claim 14 ,
 Wherein the first double-fin device comprises a first threshold voltage,   Wherein the second double-fin device comprise a second threshold voltage different from the first threshold voltage.   
     
     
         16 . A semiconductor device, comprising:
 a first fin and a second fin rising from a substrate and extending lengthwise along a first direction;   a gate structure wrapping over channel regions of the first fin and the second fin and extending along a second direction perpendicular to the first direction;   a first source/drain feature over a source/drain region of the first fin; and   a second source/drain feature over a source/drain of the second fin,   wherein the first fin bends away from the second fin along the second direction and the second fin bends away from the first fin for a first bending amount along the second direction,   wherein the first source/drain feature and the second source/drain feature bend away from one another for a second bending amount along the second direction,   wherein the second bending amount is greater than the first bending amount.   
     
     
         17 . The semiconductor device of  claim 16 ,
 wherein the first bending amount is between about 0.3 nm and about 1.5 nm,   wherein the second bending amount is between about 0.3 nm and about 3.0 nm.   
     
     
         18 . The semiconductor device of  claim 16 , further comprising:
 a first isolation feature adjacent to the first fin and away from the second fin;   a second isolation feature disposed between the first fin and the second fin; and   a third isolation feature adjacent to the second fin and away from the first fin,   wherein a top surface of the second isolation feature is lower than top surfaces of the first isolation feature and the third isolation feature.   
     
     
         19 . The semiconductor device of  claim 18 , further comprising:
 a third fin spaced apart from the first fin by the first isolation feature,   wherein a width of the first isolation feature along the second direction is greater than a width of the second isolation feature along the second direction.   
     
     
         20 . The semiconductor device of  claim 17 , wherein the first fin and the second fin comprise germanium.