Power semiconductor device and power module

Abstract

In at least one embodiment, the power semiconductor device (1) comprisesa semiconductor body (2), anda protection layer (3) at the semiconductor body (2), whereinthe protection layer (3) comprises a material having a surface energy of at most 0.1 mJ/m2, andthe protection layer (3) comprises a geometric structuring (33) having a feature size (F) of at least 0.04 μm and of at most 0.1 mm, seen in top view of the protection layer (3).

1 . A power semiconductor device comprising:
 a semiconductor body, and   a protection layer at the semiconductor body,   wherein   the protection layer comprises a material having a surface energy of at most 0.1 mJ/m2, and   the protection layer comprises a geometric structuring having a feature size of at least 0.04 μm and of at most 0.1 mm, seen in top view of the protection layer, and   the protection layer comprises as base layer, and wherein a plurality of spacer bodies is applied on the base layer.   
     
     
         2 . The power semiconductor device according to  claim 1 , wherein at least one of
 the protection layer covers a top side of the semiconductor body that is a main side thereof, the top side is provided with at least one electric contact area, and   a contact angle of the protection layer with clean water, at 300 K and 1013 hPa in air, is at least 150°.   
     
     
         3 . The power semiconductor device according to  claim 1 , wherein the geometric structuring comprises a plurality of pillars, and wherein a height of the pillars exceeds a diameter of the pillars by at least a factor of 30 and by at most a factor of 300. 
     
     
         4 . The power semiconductor device according to  claim 1 , wherein the geometric structuring comprises at least one grid formed by walls, a height of the at least one grid exceeds a width of the walls by at least a factor of 5 and by at most a factor of 200. 
     
     
         5 . (canceled) 
     
     
         6 . The power semiconductor device according to  claim 1 , wherein at least one of
 the protection layer is directly applied on the semiconductor body, and   the protection layer is electrically insulating.   
     
     
         7 . The power semiconductor device according to  claim 1 , wherein the protection layer is distant from the semiconductor body, and wherein at least one electrically insulating and continuous passivation layer is located between the semiconductor body and the protection layer. 
     
     
         8 . The power semiconductor device according to  claim 1 , wherein the protection layer comprises at least one organic material. 
     
     
         9 . The power semiconductor device according to  claim 1 , wherein the protection layer comprises at least one inorganic material. 
     
     
         10 . The power semiconductor device according to  claim 1 , wherein the geometric structuring is of regular fashion. 
     
     
         11 . The power semiconductor device according to  claim 1 , wherein the geometric structuring is of irregular fashion. 
     
     
         12 . The power semiconductor device according to  claim 1 , wherein the feature size is at least 0.5 μm and at most 3 μm. 
     
     
         13 . The power semiconductor device according to  claim 1 , wherein the power semiconductor device is a transistor configured for a current of at least 10 A and for a voltage of at least 0.6 kV. 
     
     
         14 . The power semiconductor device according to  claim 1 , wherein the power semiconductor device is part of a power module comprising
 a base plate on which the power semiconductor device is mounted, and   an encapsulation layer in direct contact with the protection layer.   
     
     
         15 . (canceled) 
     
     
         16 . A method for producing a power module comprising a base plate on which a power semiconductor device is mounted, and an encapsulation layer in direct contact with a protection layer of the power semiconductor device, the power semiconductor device comprising a semiconductor body, and the protection layer at the semiconductor body, wherein the protection layer comprises a material having a surface energy of at most 0.1 mJ/m2, and the protection layer comprises a geometric structuring having a feature size of at least 0.04 μm and of at most 0.1 mm, seen in top view of the protection layer, and the protection layer comprises a base layer, and wherein a plurality of spacer bodies is applied on the base layer, wherein the method comprises:
 providing the at least one semiconductor body; 
 applying the protection layer on the at least one semiconductor body; 
 arranging the at least one power semiconductor device on the base plate that comprises a first electric wiring to electrically contact the at least one power semiconductor device; and 
 encapsulating the at least one power semiconductor device with the encapsulation layer which forms a hull around the at least one power semiconductor device to protect the at least one power semiconductor device against environmental influences, the encapsulation layer is of a hydrophobic material.