Microelectronic assemblies

Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

1 . A microelectronic assembly, comprising:
 a redistribution layer comprising conductive traces and conductive vias;   a double-sided die having a top side and a bottom side, the bottom side on a portion of the redistribution layer, and the double-sided die having a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, the double-sided die having conductive contacts on the top side, and the double-sided die having through silicon vias (TSVs) coupled to conductive traces of the portion of the redistribution layer beneath the double-sided die;   a conductive via laterally spaced apart from the first sidewall of the first die;   a second die over the double-sided die and over the conductive via, the second die coupled to the conductive contacts on the top side of the double-sided die by first interconnects, and the second die coupled to the conductive via;   an underfill material vertically between the second die and the double-sided die, the underfill material laterally surrounding the first interconnects; and   second interconnects beneath and coupled to the redistribution layer, a portion of the second interconnects vertically beneath the double-sided die, the second interconnects comprising solder.   
     
     
         2 . The microelectronic assembly of  claim 1 , wherein the second die is coupled to all of the conductive contacts on the top side of the double-sided die. 
     
     
         3 . The microelectronic assembly of  claim 1 , wherein the underfill material comprises an epoxy. 
     
     
         4 . The microelectronic assembly of  claim 1 , wherein the second interconnects further comprise copper pillars, and wherein the solder is on the copper pillars. 
     
     
         5 . The microelectronic assembly of  claim 1 , wherein the double-sided die has a footprint entirely within a footprint of the second die. 
     
     
         6 . The microelectronic assembly of  claim 1 , further comprising:
 a third die laterally spaced apart from the double-sided die.   
     
     
         7 . The microelectronic assembly of  claim 1 , further comprising:
 a package substrate beneath and coupled to the second interconnects.   
     
     
         8 . A microelectronic assembly, comprising:
 a first insulating material having one or more conductive pathways;   a first die on a portion of the first insulating material having one or more conductive pathways, the first die having conductive contacts on a top side of the first die, and the first die having through substrate vias coupled to conductive pathways of the portion of the first insulating material having one or more conductive pathways;   a conductive via laterally spaced apart from the first die;   a second die over the first die and over the conductive via, the second die coupled to the conductive contacts on the top side of the first die by first interconnects, and the second die coupled to the conductive via;   a second insulating material vertically between the second die and the first die, the second insulating material laterally surrounding the first interconnects; and   second interconnects beneath and coupled to the first insulating material having one or more conductive pathways, a portion of the second interconnects vertically beneath the first die.   
     
     
         9 . The microelectronic assembly of  claim 8 , wherein the second die is coupled to all of the conductive contacts on the top side of the first die. 
     
     
         10 . The microelectronic assembly of  claim 8 , wherein the second insulating material comprises an epoxy. 
     
     
         11 . The microelectronic assembly of  claim 8 , wherein each of the second interconnects comprises a copper pillar with a solder cap. 
     
     
         12 . The microelectronic assembly of  claim 8 , wherein the first die has a footprint entirely within a footprint of the second die. 
     
     
         13 . The microelectronic assembly of  claim 8 , further comprising:
 a third die laterally spaced apart from the first die.   
     
     
         14 . The microelectronic assembly of  claim 8 , further comprising:
 a package substrate beneath and coupled to the second interconnects.   
     
     
         15 . A system, comprising:
 a board; and   a microelectronic assembly coupled to the board, the microelectronic assembly, comprising:
 a redistribution layer comprising conductive traces and conductive vias; 
 a double-sided die having a top side and a bottom side, the bottom side on a portion of the redistribution layer, and the double-sided die having a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, the double-sided die having conductive contacts on the top side, and the double-sided die having through silicon vias (TSVs) coupled to conductive traces of the portion of the redistribution layer beneath the double-sided die; 
 a conductive via laterally spaced apart from the first sidewall of the first die; 
 a second die over the double-sided die and over the conductive via, the second die coupled to the conductive contacts on the top side of the double-sided die by first interconnects, and the second die coupled to the conductive via; 
 an underfill material vertically between the second die and the double-sided die, the underfill material laterally surrounding the first interconnects; and 
 second interconnects beneath and coupled to the redistribution layer, a portion of the second interconnects vertically beneath the double-sided die, the second interconnects comprising solder. 
   
     
     
         16 . The system of  claim 15 , further comprising:
 a memory coupled to the board.   
     
     
         17 . The system of  claim 15 , further comprising:
 a communication chip coupled to the board.   
     
     
         18 . The system of  claim 15 , further comprising:
 a display device coupled to the board.   
     
     
         19 . The system of  claim 15 , further comprising:
 a GPS device coupled to the board.   
     
     
         20 . The system of  claim 15 , further comprising:
 a battery coupled to the board.