Performance and area efficient synapse memory cell structure

Abstract

A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

What is claimed is: 
     
         1 . A synapse memory system, comprising:
 an analog memory, comprising:
 a free layer, the free layer including fixed regions disposed at end portions thereof and a data region interposed between the fixed regions; and 
 a plurality of pinning layers disposed on each respective fixed region, 
 wherein excitation of the fixed regions by the pinning layers induces opposed magnetic fields in each respective fixed region, the opposed magnetic fields defining a domain wall at an inflection point of the opposed magnetic fields of the fixed regions. 
   
     
     
         2 . The synapse memory system according to  claim 1 , wherein a length of the analog memory is greater than a width of the analog memory, the length and width of the analog memory defining an aspect ratio. 
     
     
         3 . The synapse memory system according to  claim 2 , wherein the aspect ratio of the analog memory is large. 
     
     
         4 . The synapse memory system according to  claim 1 , wherein the analog memory is incorporated within a synapse memory cell. 
     
     
         5 . The synapse memory system according to  claim 4 , wherein dynamic ranges of a plurality of analog memories are combined to obtain a dynamic range of the synapse memory cell as a whole. 
     
     
         6 . The synapse memory system according to  claim 4 , wherein an aspect ratio of each synapse memory cell is smaller than an aspect ratio of each analog memory. 
     
     
         7 . The synapse memory system according to  claim 4 , wherein an aspect ratio of each synapse memory cell is almost 1:1. 
     
     
         8 . The synapse memory system according to  claim 1 , wherein each analog memory is a non-volatile random access memory (NVRAM). 
     
     
         9 . An analog memory for use in a synapse memory cell, comprising:
 a free layer, the free layer including fixed regions disposed at end portions thereof and a data region interposed between the fixed regions; and   a plurality of pinning layers disposed on each respective fixed region,   wherein excitation of the fixed regions by the pinning layers induces opposed magnetic fields in each respective fixed region, the opposed magnetic fields defining a domain wall at an inflection point of the opposed magnetic fields of the fixed regions.   
     
     
         10 . The analog memory according to  claim 9 , wherein a length of the analog memory is greater than a width of the analog memory, the length and width of the analog memory defining an aspect ratio. 
     
     
         11 . The analog memory according to  claim 10 , wherein the aspect ratio of the analog memory is large. 
     
     
         12 . The analog memory according to  claim 9 , wherein the analog memory is incorporated within a synapse memory cell. 
     
     
         13 . The analog memory according to  claim 12 , wherein dynamic ranges of a plurality of analog memories are combined to obtain a dynamic range of the synapse memory cell as a whole. 
     
     
         14 . The analog memory according to  claim 12 , wherein an aspect ratio of the synapse memory cell is smaller than an aspect ratio of the analog memory. 
     
     
         15 . The analog memory according to  claim 12 , wherein an aspect ratio of the synapse memory cell is almost 1:1. 
     
     
         16 . The analog memory according to  claim 9 , wherein each analog memory is a non-volatile random access memory (NVRAM). 
     
     
         17 . A synapse memory system, comprising:
 a synapse memory, comprising:
 a plurality of synapse memory cells disposed at cross points of a plurality of axon lines and a plurality of dendrite lines, wherein a length of the synapse memory along an axon line portion compared to a length of the synapse memory along a dendrite line portion defines an aspect ratio; 
   a first plurality of peripheral devices operably coupled to the axon line portion of the synapse memory; and   a second plurality of peripheral devices operably coupled to the dendrite line portion of the synapse memory,   wherein the aspect ratio of the synapse memory approximates 1:1.   
     
     
         18 . The synapse memory system according to  claim 17 , further comprising a plurality of synapse memories, wherein each synapse memory includes a synapse memory cell where a plurality of synapse memory cells are arranged such that a long side of each is disposed parallel to one another such that the aspect ratio of the synapse memory cell approximates 1:1. 
     
     
         19 . The synapse memory system according to  claim 17 , wherein each synapse memory cell includes analog memory. 
     
     
         20 . The synapse memory system according to  claim 19 , wherein the analog memory includes a non-volatile random access memory (NVRAM).