Overflow detection and correction in state machine engines

Abstract

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

What is claimed is: 
     
         1 . A data analysis system, comprising:
 a data buffer configured to receive data to be analyzed;   a state machine lattice comprising a plurality of configurable elements, wherein the configurable elements are configured to analyze at least a portion of the data as an analysis and to output a result of the analysis; and   a buffer interface configured to receive the data from the data buffer and to provide the at least a portion of the data to the state machine lattice for analysis.   
     
     
         2 . The data analysis system of  claim 1 , comprising a second plurality of configurable elements configured to receive the result from the plurality of configurable elements. 
     
     
         3 . The data analysis system of  claim 2 , wherein the second plurality of configurable elements are configured to analyze at least a portion of the result and to output a second result based upon analysis of the result. 
     
     
         4 . The data analysis system of  claim 3 , comprising a second data buffer configured to receive the second result from the second plurality of configurable elements. 
     
     
         5 . The data analysis system of  claim 1 , comprising a second data buffer configured to receive the result from the plurality of configurable elements. 
     
     
         6 . The data analysis system of  claim 1 , comprising a host processor configured to receive the result from the plurality of configurable elements. 
     
     
         7 . The data analysis system of  claim 1 , wherein each configurable element of the plurality of configurable elements comprises a plurality of memory cells. 
     
     
         8 . A method, comprising:
 receiving, at a buffer interface, data to be analyzed from a data buffer;   providing at least a portion of the data to a state machine lattice via the buffer interface;   analyzing the at least a portion of the data in a first set of configurable elements of the state machine lattice to generate a result; and   outputting the result from the configurable elements of the state machine lattice.   
     
     
         9 . The method of  claim 8 , comprising receiving the result from the first set of configurable elements of the state machine lattice at the buffer interface and outputting the result from the buffer interface. 
     
     
         10 . The method of  claim 9 , comprising receiving the result from the buffer interface at a second data buffer. 
     
     
         11 . The method of  claim 8 , comprising receiving the result at a second set of configurable elements. 
     
     
         12 . The method of  claim 8 , comprising receiving the result at a host processor. 
     
     
         13 . The method of  claim 8 , comprising utilizing a plurality of memory cells of the first set of configurable elements to generate the result. 
     
     
         14 . A system, comprising:
 a host processor configured to initiate transmission of data to be analyzed;   a data buffer configured to transmit the data to be analyzed;   a buffer interface configured to receive the data from the data buffer; and   a state machine lattice coupled to the buffer interface to receive the at least a portion of the data, wherein the state machine lattice is configured to analyze the at least a portion of the data and to output a result.   
     
     
         15 . The system of  claim 14 , wherein the state machine lattice comprises a plurality of configurable elements. 
     
     
         16 . The system of  claim 15 , wherein each configurable element of the plurality of configurable elements comprises a memory cell. 
     
     
         17 . The system of  claim 15 , wherein the state machine lattice comprises a second plurality of configurable elements configured to receive the at least a partial analysis result from the plurality of configurable elements, wherein the second plurality of configurable elements is configured to perform an analysis based at least in part on the partial analysis result to generate the result. 
     
     
         18 . The system of  claim 14 , comprising a second data buffer configured to receive the result from the state machine lattice. 
     
     
         19 . The system of  claim 14 , wherein the host processor is configured to receive the result from the state machine lattice. 
     
     
         20 . The system of  claim 14 , wherein the data buffer is configured to receive and store the data to be analyzed.